2020 Volume 63 Issue 3 Pages 123-128
A new computing architecture, an annealing machine, which is specialized to solve combinatorial optimization problems, is proposed. The annealing machine maps combinatorial optimization problems to an Ising model and solves the problems by its own convergence property. We proposed a CMOS annealing machine, which is a CMOS implementation of the annealing machines. The CMOS annealing machine has an in-memory computing architecture for a high scalability. We constructed prototypes of the CMOS annealing machine. The 1st generation prototype with ASIC implementation, the 2nd generation prototype with FPGA implementation and the card-size prototype with 2-chip ASIC implementation are used to confirm its ability to solve combinatorial optimization problems and its high energy efficiency. The 2nd and card-size prototypes also confirm its multiple-chip operation, which enables a higher scalability of the CMOS annealing machine solving larger size optimization problems.
