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The 26th JIEP Annual Meeting

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The 26th JIEP Annual Meeting

Connectiing Structure between Rigid PCB and Flexible PCB

Keitaro Yamagishi, Takuma Ishibashi, Koji Shibuya, Hideyuki Ohashi

Session ID: 7A-01
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_1

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Verification of 2.5D, 3D electromagnetic simulations for high speed interface package

Toshiki Iwai, Yoshiyuki Kimura, Yoshihiko Ikemoto, Atsushi Sato, Takes ...

Session ID: 7A-02
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_3

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The influence of package inner trace in the transmission line simulation of high-speed signals

Xianzheng Wang, Hitoshi Miwa, Kiyohisa Hasegawa, Atushi Owaki

Session ID: 7A-03
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_6

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Waveform Improvement Methods for High-speed Digital Signal Transmission

Moritoshi Yasunaga

Session ID: 7A-04
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_8

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In the GHz domain, the conventional impedance matching techniques willnot do their works in the SI improvement any longer. In order toovercome this difficulty, we proposed a novel technique based onimpedance mismatching, where a trace are divided into multiplesegments of individual characteristic impedances and the reflectedwaves occurred at their boundaries are superposed on the distortedwave to improve its waveform. We apply this method to traces in somememory bus systems and demonstrate its remarkable effectiveness on theSI improvement using some prototypes.

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Regarding the consideration of the next generation's super-high-speed long reach transmission

Makoto Suwada

Session ID: 7A-05
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_12

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Recently, the speed-up of the long reach transmission in information and telecommunications equipments are very remarkable as 10GBASE-KR. Then, we describe the consideration regarding the next generation's super-high-speed long reach transmission that will become more speed-up.

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Design Method for Impedance Matching

Shinichi Maeda

Session ID: 7A-06
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_14

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It is important to match the characteristics impedance of the over 5GHz signals. The connector pads and via have the different shape form other etch line area and difficult to match the impedance. In usual, the 3-D field solver is used for the design foot the pad and via. By the way, the characteristic of PCB material has a little tolerance between given data which is used to 3-D simulation and actual material. It makes the small impedance mismatch. This paper shows that how to get the actual material characteristics from actual PWB and use this value for 3-D simulation.

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Studies on resin hardening behavior in low melting point metal/epoxy resin solder pastes

Kazuhiro Kitamura, Keishiro Okamoto, Nobuhiro Imaizumi, Tomohisa Yagi, ...

Session ID: 7B-01
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_18

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Effect of Ni content on growth of the reaction layer formed in the Sn-Cu-Bi/Cu substrate interface during bonding

Tomoya Yokota, Kazuya Kurokawa, Jyunnichi Tanaka

Session ID: 7B-02
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_20

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the behavior and the friction among CNT during the compression of VACNT bumps

Hidenori Terasaka, masahisa Fujino, Tadatomo Suga, Ikuo Soga, Daiyuu K ...

Session ID: 7B-03
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_24

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Surface Activated Bonding and Transfer of Vertically Aligned Carbon Nanotubes to Au substrate mediating Au sptter layer

Masahisa Fujino, Hidenori Terasaka, Tadatomo Suga, Ikuo Soga, Daiyu Ko ...

Session ID: 7B-04
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_26

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Next Generation Power Device Module and Polymer Materials

Akio Takahashi

Session ID: 7B-05
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_28

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Power semiconductor devices are key devices for carbon dioxide reduction technology.Here, we focus on the power semiconductor device module of automotive electronics field holding more than 50% of the power device market and introduce the optimum properties and the examples for polymer materials applying to the future power module.

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Study on bismaleimide resin cured by phenolic resins

Reo Takaiwa, Toshiyuki Oyama, Akio Takahashi

Session ID: 7B-06
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_32

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Fabrication of Lead-free Dielectric Thin Film on Releasable Substrate

Motoyuki Ozaki, Toshifumi Hosono, Masaaki Ichiki, Tadatomo Suga, Toshi ...

Session ID: 7C-01
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_34

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Improving the Quality of Dielectric Film and the Application to Wafer Level Film Preparation

Kazutaka Sueshige, Keita Iimura, Masaaki Ichiki, Tadatomo Suga, Toshih ...

Session ID: 7C-02
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_37

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Preparation and characterization of PZT thin films on releasable substrate

Erika Komine, Fumiaki Tomioka, Masaaki Ichiki, Tadatomo Suga, Toshihir ...

Session ID: 7C-03
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_39

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Silicone elastomer contact structure for woven electronic textile

Takahiro Yamashita, Koji Miyake, Toshihiro Itoh

Session ID: 7C-04
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_41

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Highly sensitive two-dimensional strain distribution sensor using carbon nanotubes

Yusuke Suzuki, Ken Suzuki, Hideo Miura

Session ID: 7C-05
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_43

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Three dimensional micro/nanowire arrays for sensing applications

Takeshi Kawano

Session ID: 7C-06
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_47

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Discussions on Precise Measurement of Planar Anisotropic Complex Permittivity for a Liquid Crystal Polymer Film

Yoshio Kobayashi, Shuhei Wadayama, Zhewang Ma

Session ID: 8A-01
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_49

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Improvement of dielectric property of liquid crystal polymer films as circuit material

Minoru Onodera, Tatsuya Sunamoto, Shuhei Wadayama, Yoshio Kobayashi

Session ID: 8A-02
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_51

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Liquid crystal polymer film Vecstar CT-Z has the highest level of solder resistance and high-speed transmission properties among commercially LCP films. This report explains a measurement method and an improvement method about the uniformity of the dielectric characteristic.

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Measurement of surface and interface conductivity of copper-clad dielectric laminated substrates in the frequency range 1~20GHz

Masayuki Tsunemitsu, Yoshio Kobayashi, Zhewang Ma

Session ID: 8A-03
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_53

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Measurements of Complex Permittivity in the range 1 to 10GHz Using a Balanced-type Circular Disk Resonator

Yoshio Kobayashi, Shogo Kaneko, Zhewang Ma

Session ID: 8A-04
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_55

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MULTI-PRIDE: A System for Supporting Multi-Layered Printed Wiring Board Design

Daisuke Takafuji, Toshimasa Watanabe

Session ID: 8A-05
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_57

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Far-end Crosstalk Reduction Techniqe for Printed Circuit Board using Patch Capacitors

Shinichi Sasaki

Session ID: 8A-06
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_61

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A Study of Miniature Via-less EBG Structure - Application of Metamaterial Technology

jun kamiya, Kenichi Shirota, Takahiro Yagi, Tetsuo Nakazawa

Session ID: 8A-07
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_63

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The Noise Suppression Technology, by using EBG Structure applying Metamaterial Technology. We reported Miniature Via-less EBG Structure with a stopband below 2GHz.In this paper,We report further miniaturization and flexibility of Miniature Via-less EBG Structure.

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Consideration for reducing the noise currents flowing through signal and ground patterns of PCB for vehicle-mounted electronic equipment

Tsuyoshi Maeno, Michihira Iida

Session ID: 8A-08
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_65

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Noise Reduction and Signal Transmission Characteristics of A Common-mode Noise Filter for Differential Signaling

Naoto Oka, Satoshi Yoneda, Koichiro Misu, Seiichi Saito

Session ID: 8A-09
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_69

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Circuit Analysis of Signal Transmission Systems with Mode-equivalent Circuit Based on Mode-decomposition Technique

Yoshitaka Toyota, Kota Sejima, Kengo Iokibe, Liuji R. Koga, Tetsushi W ...

Session ID: 8A-10
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_72

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Noise Immunity to the Connector Grounding of the Balanced Cable with Shielded Sheath

Yosuke Watanabe, Yuichi Sasaki, Chiharu Miyazaki, Naoto Oka, Koichiro ...

Session ID: 8A-11
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_76

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Recently, high-speed differential transmission system is expanding application, it is important to study the noise immunity of a balanced cable. In order to improve the noise immunity, a balanced cable with a shielded sheath is used. But if the shielding and the grounding of a shield sheath are imperfect, the noise immunity of the whole system may degrade. In this report, we study about the evaluation result of the noise immunity on the shield condition of the shielded twisted pair cable.

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Study of high-speed copper cable structure with one batch extruded insulator for 25Gbit/s transmission

Takahiro Sugiyama, Hideki Nonen, Takashi Kumakura

Session ID: 8A-12
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_78

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Method of Local Immunity Efficiency Evaluation

Yukihiko Sakurai, Kouji Ichikawa, Isao Iwase

Session ID: 8A-13
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_80

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Measurement and analysis of SSN and jitter of FPGA

Haruya Fujita, Koji Sakuma, Yoh Iijima, Toshio Sudo

Session ID: 8A-14
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_82

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The measures to suppress the EMI noise from the high speed data card circuit in electronic devices

Kota Saito, Hiroyuki Takatsuji, Ken Takakura, Naoki Iida, Masahiko Kaw ...

Session ID: 8A-15
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_84

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Immunity Evaluation Method for High-speed Signal Transmission using Transient Analysis

Yusuke Suzuki, Yoshihiro Akeboshi, Naoto Oka, Hideyuki Ohashi, Seiichi ...

Session ID: 8A-16
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_88

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Study on Supply Noise Reduction Effect using Decoupling Capacitor with Resistor

Jun Saitou, Yukio Tani, Takehiro Takahashi, Noboru Shibuya

Session ID: 8A-17
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_90

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Combinatorial use of low- and high-series resistance capacitors for reducing impedance of power supply network

Koh Yamanaga, Takashi Sato

Session ID: 8A-18
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_94

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Anti-resonance of PDN (Power Distribution Network) impedance often induces power supply voltage fluctuation and deteriorates stability and performance of LSI. According to the tendency of low operating voltage, PDN design considering anti-resonance becomes very important. In this paper, we propose efficient reduction method of anti-resonance of PDN using combination of low and high ESR (Equivalent Series Resistor) capacitors. We experimentally show that our method improves the demerits of conventional methods that use each capacitor only, and reduce PDN-impedance efficiently.

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Enhancement of ICs in EMC Performance by Use of Critical Damping of Power Distribution Network Resonance

Kengo Iokibe, Yusuke Yano, Yoshitaka Toyota

Session ID: 8A-19
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_98

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A Practical Examination of Chip-Package-PCB Co-design for LSI Operation Stability

Hiroyuki Motoki, Hideyuki Nakanishi, Akihiro Tanaka, Kenji Wada, Tadas ...

Session ID: 8A-20
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_102

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Data format development for device embedded substrates

Hajime Tomokage

Session ID: 8B-01
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_106

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Active and passive devices are embedded inside the substrate in order to make high density packaging. The device embedded substrate technology is one of the three dimensional integration technologies. Since the interconnection point of embedded devices must be defined three-dimensionally for manufacturing process, a new data format "FUJIKO" has been developed for device embedded substrate as well as three dimensional system-in-a-package. It enables one to send design data to manufacturing and test equipment quickly with high accuracy.

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The present conditons of Embedded Technology and futuer subject

hiroshi iinaga

Session ID: 8B-02
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_109

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Consideration of the structure and the function for Device Embedded substrate

Koji Ikawa

Session ID: 8B-03
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_110

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IC Embedded Package using Polyimide Multilayer Board

Masahiro Okamoto, Kazuhisa Itoi, Nobuki Ueta, Shin Hitaka, Satoshi Oku ...

Session ID: 8B-04
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_113

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Quality Management of Engineering Simulation

Masaki Shiratori

Session ID: 8B-05
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_115

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Debonding Strength Evaluation Based on the Intensity of Singular Stress (Part 1:Analysis Method)

Nao-Aki Noda, Keen-Taro Takaishi, Zhang Yu, Xin Lan, Yasushi Takase, Y ...

Session ID: 8B-06
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_119

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Debonding Strength Evaluation Based on the Intensity of Singular Stress (Part 2:Discussion of Experimental Results)

Nao-Aki Noda, Kengo Michnaka, Xin Lan, Zhang Yu, Yasushi Takase, Yoshi ...

Session ID: 8B-07
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_123

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Moisture Absorption Behaviors of Transfer-molded Power Modules with Insulating Resin Sheet

Kei Yamamoto, Hiroyuki Harada, Xiaohong Yin, Kenji Mimura, Takashi Nis ...

Session ID: 8B-08
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_127

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TEM analysis of a soldering

Yoshihiko Seyama, Takahashi Nobuo, Kuribara Jou

Session ID: 8B-09
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_129

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Three-dimensional and nondestructive evaluation of thermal fatigue crack propagation process in solder joints of different-sized resistor

Yoshiyuki Okamoto, Takeshi Takayanagi, Hiroyuki Tsuritani, Toshihiko S ...

Session ID: 8B-10
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_131

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Nondestructive Observation of Thermal Fatigue Cracks in PCB's Solder Joints by Synchrotron Radiation X-Ray Laminography

Hiroyuki Tsuritani, Toshihiko Sayama, Yoshiyuki Okamoto, Takeshi Takay ...

Session ID: 8B-11
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_134

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Analysis of Microstructural Coarsening for Sn-Ag-Cu by Strain-enhanced Growth Model and its Application to Evaluation of Fatigue Reliability

Yoshihiko Kanda, Yoshiharu Kariya, Takeshi Tasaka

Session ID: 8B-12
Published: 2012
Released on J-STAGE: July 17, 2014

DOIhttps://doi.org/10.11486/ejisso.26.0_137

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