IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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Volume 1, Issue 12
Displaying 1-6 of 6 articles from this issue
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LETTER
  • Planar arrayed waveguide device structure for 2D wavelength demultiplexing
    Hideaki Okayama
    2004 Volume 1 Issue 12 Pages 322-327
    Published: 2004
    Released on J-STAGE: September 25, 2004
    DOIhttps://doi.org/10.1587/elex.1.322
    JOURNAL FREE ACCESS
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    Simple arrayed waveguide grating (AWG) structure which demultiplexes wavelengths to output ports arranged in 2D plane is proposed. The planar geometry provides easy fabrication of the device. An AWG is connected to a device forming a 2D aperture array, which generates smaller dispersion in orthogonal direction against that generated by AWG.
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  • Virtual topology design issues for variable traffic
    T. Wauters, D. Colle, E. Van Breusegem, S. Verbrugge, S. De Maesschalc ...
    2004 Volume 1 Issue 12 Pages 328-332
    Published: 2004
    Released on J-STAGE: September 25, 2004
    DOIhttps://doi.org/10.1587/elex.1.328
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    This paper discusses and evaluates, in terms of number of wavelength channels and router port count, different grooming strategies exploiting the benefits of statistical multiplexing. For the network design, a hybrid solution, combining the advantages of both the end-to-end and the link-by-link grooming scenario, is proposed.
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  • A low-jitter phase-interpolation DDS using dual-slope integration
    Hsin-Chuan Chen, Jen-Shiun Chiang
    2004 Volume 1 Issue 12 Pages 333-338
    Published: 2004
    Released on J-STAGE: September 25, 2004
    DOIhttps://doi.org/10.1587/elex.1.333
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    In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.
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  • Biasing CMOS amplifiers using MOS transistors in subthreshold region
    Manoj Bikumandla, Jaime Ramírez-Angulo, Carlos Urquidi, Ramon G ...
    2004 Volume 1 Issue 12 Pages 339-345
    Published: 2004
    Released on J-STAGE: September 25, 2004
    DOIhttps://doi.org/10.1587/elex.1.339
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    The implementation of large-valued floating resistive elements using MOS transistors in subthreshold region is addressed. The application of these elements to bias wideband AC coupled amplifiers is discussed. Simple schemes to generate the gate control voltages for the MOS transistors implementing large resistors so that they remain in high resistive state with large signal variations are discussed. Experimental results of a test chip prototype in 0.5-µm CMOS technology are presented that verify the proposed technique.
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  • Miniaturized ultrahigh frequency fundamental quartz resonators
    Hirokazu Iwata
    2004 Volume 1 Issue 12 Pages 346-351
    Published: 2004
    Released on J-STAGE: September 25, 2004
    DOIhttps://doi.org/10.1587/elex.1.346
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    I fabricated an inverted-mesa quartz resonator having a 2.2-µm-thick vibrating area by wet etching. The resonator excited a 622-MHz-fundamental thickness vibration. By selecting a 30-nm-thick gold electrode, the temperature-frequency characteristics exhibited a cubic curve with a frequency deviation of 26ppm over a range of temperature from -40°C to +85°C. Furthermore, the resonator was miniaturized to reduce loss caused by the film resistance, and to decrease the parallel capacitance. The series resistance at the noninductive resonance frequency was 33ohm and the parallel capacitance was 0.96pF. Therefore, the fundamental thickness vibration had a wide inductive region.
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  • A fast encoding algorithm for fractal image compression
    Chou-Chen Wang, Jung-Yang Kao
    2004 Volume 1 Issue 12 Pages 352-357
    Published: 2004
    Released on J-STAGE: September 25, 2004
    DOIhttps://doi.org/10.1587/elex.1.352
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    The major drawback of the fractal image compression is the high encoding complexity to find the best match between a range block and a large pool of domain blocks. This paper presents a fast fractal-encoding algorithm based on the law of cosines. The number of domain blocks searched to find the best match for each range block is safely reduced by eliminating the ineligible domain blocks using the law of cosines. Simulation results show that the proposed algorithm can produce a completely identical fractal code to that of the exhaustive search in reduced time.
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