In this express, we propose an improved architecture for modulo (2ⁿ+3) multiplication on the condition n≥6. With this architecture, we can design the fastest among all known modulo (2ⁿ+3) multipliers. The proposed modulo (2ⁿ+3) multiplier can improve the state-of-art by 3.2% on the average in terms of area and 10.1% on the average in terms of performance delay.

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This paper describes a RTS (random telegraph signal) noise reduction technique for an active pixel CMOS image sensor (CIS) with in-pixel selectable dual source-follower amplifiers. In this CMOS image sensor, the lower-noise transistor in each pixel is selected in the readout operation using a table of determining the lower-noise transistors of all the pixels. A prototype image sensor with 65×290 pixels for demonstrating the effectiveness of this technique has been implemented using 0.18µm CMOS image sensor technology with pinned photodiode option. The measured result shows that the maximum noise using the amplifier-selection technique is reduced to 9.6e- from 17.2e- which is the maximum noise of the image array using one of two amplifiers in each pixel without selection.

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A cavity-resonator-integrated guided-mode resonance filter (CRIGF) consisting of a grating coupler and a pair of distributed Bragg reflectors in a channel waveguide is proposed for a narrow-band reflection spectrum with a small aperture. A channel waveguide structure and grating pattern of the device were simultaneously formed by the electron-beam direct-writing lithography. A full-width at half-maximum of reflection spectrum of the fabricated CRIGF was about 0.3nm with the maximum reflectance of about 30%. A reflection phase varied by almost 2π for wavelength change of 1nm.

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A micromachined capacitive pressure sensor with a single crystal silicon membrane and wafer-through silicon via electrodes embedded in the glass substrate is demonstrated. SOI (silicon-on-insulator)-Si direct wafer bonding and reflow technique of the bonded glass wafer are combined to fabricate the pressure sensor. The proposed process enables to access the sensing capacitor easily from the backside of the substrate without bondwires on the front, and helps to achieve uniform sensor performances thanks to the uniform thickness of the SOI device layer. The fabricated sensors show an initial capacitance of 7.68±0.39pF with an averaged sensitivity of 1.29±0.06fF from 0 to 360 Torr.

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In this communication, we present the design of a compact, asymmetric coplanar strip (ACS)-fed, dual-band antenna for WLAN communication applications that is based on the use of loaded capacitance termination technique. The design procedure and the effects of the loaded capacitance terminations on the performance are described and investigated. The designed antenna has an electrically small size and its two resonance frequencies are realized by using two meander line monopole antennas with loaded capacitance terminations. The measurement results show that the antenna has impedance bandwidths of 168MHz and 187MHz, respectively, for operating frequencies of 2.4GHz and 5.8GHz.

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Dual-addressing memory architecture is designed for two-dimensional memory access with both row-major and column-major localities. In this paper, we highlight two memory management issues in dual-addressing memory. First, to avoid the external fragmentation, we propose a virtual dual-addressing memory design to enable memory management via operating system. After that, to deal with the size mismatch between user-defined data and dual-addressing memory, we discuss data arrangement policies at different data granularity. With the proposed memory management techniques, we are capable of maximizing the memory utilization of dual-addressing memory.

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It is becoming common to implement power switches in low power system-on-chip (SoC). However, the power switches are not tested for manufactory defects in most designs currently. In this letter, a novel built-in self test (BIST) solution for power switch is proposed. The proposed solution can test the power switch with complete test vectors and fewer test cycles. For m switches, it only takes m+3 cycles to complete the whole test operation. Besides, the test vectors are very simple, the test results are very easy to be identified, and the proposed BIST circuit can be scaled freely with the amount of switches. In addition, although headers are analyzed in detail in this letter, the results are equally applicable to footers.

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This paper presents a design methodology for ultra-wideband bias tees, using a distributed network synthesis considering both RF and DC performance. For the design of bias tees, transfer functions of distributed circuits are offered using equal ripple approximation, and DC current-handling capacity is incorporated into the network synthesis by calculating capacity in terms of the characteristic impedance of a transmission line. A bias-tee circuit with the desired characteristics can be synthesized by properly adjusting the minimum insertion loss (MIL) and ripple of the transfer function with reference to the required performance. As an example, a distributed network synthesis is applied to design a bias tee for ultra-wideband applications.

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A novel compression technique for modulo-normalized state metrics in turbo decoder is presented. This technique performs the compression dynamically according to the range of state metrics. The framework of the compression circuit is given. BER performances for several turbo decoders are simulated. Implementation results show that the proposed technique needs only 25.2% logic gates and 77.5% memory bits of the existing method with same BER performance loss and much shorter critical path for eight state turbo codes. For four state turbo codes, 30.1% logic gates and 75% memory bits are required.

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In this letter, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed FFT processor can support variable lengths of 64, 128, 256, 512, 1024, 1536 and 2048. By reducing the required number of non-trivial multipliers with a mixed-radix algorithm, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in a hardware description language (HDL) and synthesized to gate-level circuits using a 0.13µm CMOS standard cell library. With the proposed architecture, the gate count for the proposed FFT processor is 78.8K and the size of memory is 393.22Kbits, which are reduced by 40.9% and 19.7%, respectively, compared with the 4-channel radix-2 single-path delay feedback (R2SDF) with the 4-channel radix-3 SDF (R3SDF) FFT processor. Also, compared with the 4-channel radix-2 multi-path delay commutator (R2MDC) with the 4-channel R3SDF FFT processor, it is shown that the gate count and memory size are reduced by 33.8% and 18.5%, respectively.

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All-pass phase shifters using ferroelectric varactors are designed, fabricated, and measured. The design equations for the all-pass phase shifter are presented. The fabrication process of the ferroelectric varactors is described. Measurement results of single-stage all-pass phase shifters show that phase shift greater than 85° can be achieved under 10-V bias. At the frequency where maximum phase shift occurs, the insertion loss is less than 2dB and the return loss is greater than 12dB. Simulations based on the measured S parameters of the single-stage phase shifters show that, by cascading four stages of individually biased single-stage phase shifters, maximum phase shift of 180° can be achieved with a phase error as low as ±3° between 2.1GHz and 3.25GHz, corresponding to a 43% bandwidth.

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Tremendous efforts have been made to reduce the cycles per macroblock for intra prediction and transform function blocks for H.264/AVC encoders. We propose a high performance intra prediction and transform logic that can be used for all prediction cases, even when considering the interface with inter prediction results; the overall performance of the encoder is therefore ensured for real-time operation for UHD images.

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A 0.5V LC-VCO implemented in 0.18µm CMOS with a novel switched varactor technique is described in this paper. This novel switched varactor technique can increase the varactor control voltage variation range and increase Q of LC tank; also it can reduce phase noise and power consumption of VCO. Forward-body bias technique is used to reduce the threshold voltage and improve g_m of transistor. The measured operating current is 4.4mA and the tuning range is 4.6∼5.2GHz. The phase noise is −114dBc/Hz at 1MHz from carrier frequency 4.8GHz.

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