Mixed coupling modified trisection (MCMT) and its applications to substrate integrated waveguide (SIW) filters are presented. By using source or load to replace a resonator and introducing mixed coupling into conventional trisection, the proposed MCMT not only reduce one resonator but also adds a transmission zero (TZ) to improve the stopand. Moreover, the resonators in MCMT can be embedded into multilayer LTCC substrate to achieve a more compact area. Two SIW filters with two TZs are designed and fabricated to validate the proposed method. Measured results which exhibit good selectivity, agree well with simulated ones.

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A design methodology for the edge termination is proposed to achieve the same breakdown voltage of the non-uniform super-junction (SJ) trench metal-oxide semiconductor field-effect transistor (TMOSFET) cell structure. A simple analytical solution for the effect of charge imbalance on the termination region is suggested, and it is satisfied with the simulation of potential distribution. The doping concentration decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top. The structure modeling and the characteristic analyses for potential distribution and electric field are simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the breakdown voltage of 132V is successfully achieved at the edge termination of non-uniform SJ TMOSFET, which has the better performance than the conventional structure in the breakdown voltage.

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An all-digital spread-spectrum clock generator (ADSSCG) with direct modulation on the digitally controlled oscillator (DCO) is presented. The proposed ADSSCG can generate an accurate triangular modulation on the output frequency, and thus it can achieve high electromagnetic interference (EMI) reduction with a smaller spreading ratio as compared with existing designs. In addition, the proposed frequency counter-based mechanism can maintain the long-term frequency stability of the ADSSCG. The proposed ADSSCG is implemented in a standard performance 65nm CMOS process, the active area is 85μm × 85μm. It consumes 163.9μW at 270MHz with a 1.0V power supply. The EMI reduction of the proposed ADSSCG is 13.99dB with a 0.5% spreading ratio at 270MHz, and 20.23dB EMI reduction is achieved with a 1.5% spreading ratio at 162MHz. Moreover, the proposed ADSSCG is designed with standard cells, and thus it can be ported to different process in a short time.

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An integrated digital buck DC-DC converter based on a 0.5µm standard CMOS process is presented in this paper. Its switching frequency is 5MHZ and no extra high frequency clock is needed. The delay-line ADC with a self-calibration loop utilized in the converter has low sensitivity to the process, voltage, temperature and loading (PVTL). The DPWM in the proposed DC-DC converter employs a first-order Σ-Δ modulator to achieve an equivalent resolution of 10-bit. The simulation results show that the proposed DC-DC converter can operate at the supply voltage range of 2.7 to 3.6V with a transient response time of 30µs. The peak efficiency reaches 94%.

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In this letter, we proposed a new algorithm to solve the problem concerning the direction-of-arrivals (DOAs) estimation of coherently distributed sources based on the block sparse signal matrix uncertainty model of compressed sensing. Considering the measurement matrix corrupted by the unknown noise, the central DOA and the angular spread estimation may degrade considerably. But our method is robust with the measurement matrix uncertainty. Furthermore, the proposed method has better performance in low signal-to-noise (SNR). The effectiveness of our method is confirmed by simulation results.

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A self-correcting check bit generator (SCO-CBG) is proposed that can correct errors in the check bits produced by faulty check bit generator (CBG). The SCO-CBG amends check bit errors using the concept of error correction code (ECC) techniques. In the SCO-CBG, the parity bits and predicted parity bits function as the check bits of the ECC techniques. The SCO-CBG and the conventional triple modular redundancy (TMR) CBG are implemented using 45nm library. When compared with the TMR CBG, the SCO-CBG reduces the area overhead and power consumption for 128 data bit word by up to 48.4% and 47.0%, respectively.

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This paper presents a novel stereo enhancement structure for the surround stereo class-D audio amplifier. The principle of this stereo enhancement scheme has been analyzed. It shows that the amplifier with this proposed circuit have a better live effect than the traditional class-D audio amplifiers. In this circuit, the input audio signal from one channel can be amplified in the two channels at the same time, by a way of cross-coupling. The ratio of gains in the two channels also can be adjusted by changing the external resistance, which improves the stereo effect. A practical implementation in a CMOS 0.18-µm process has been done to validate the theoretical results. When a sine signal with 1KHz frequency and 100mV amplitude is applied in one channel, and a DC applied signal in the other, the amplifier demonstrates a gain difference of 9.4dB.

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Asymptotic solutions for the scattered field by a coated conducting cylinder including the scattering phenomena inside of a coating medium are presented in this paper. We derive the geometrical optics (GO) series solution including a multiply reflected GO, which is applicable in the deep lit regions far away from the geometrical boundaries (GBs) produced by the incident wave on the coated cylinder from the tangent direction. Also derived is the extended uniform geometrical theory of diffraction (UTD) series solution including a multiply reflected surface diffracted ray, which is applicable in the transition regions near the GBs and the deep shadow regions far away from the GBs. The validity of the asymptotic solutions proposed here is confirmed by comparing with the exact solution.

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This paper presents the technique to dynamically enhance the power efficiency of PWM class-D amplifier over a wide range of modulation indexes. The power stage of amplifier is segmented into several small stages and selectively enabled according to the power demand (i.e. modulation indexes). The capability of power delivery is dynamically adjusted to minimize the power loss in case of different modulation indexes improving the power efficiency, especially for small modulation index. The simulation results show that the amplifier remains high power efficiency over a wide range of modulation indexes. The maximum improvement on power efficiency is over 27% for the case of small modulation index. Moreover, for the region of power efficiency greater than 80%, the improvement is 13.5% than that of conventional design.

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In the current Dynamic voltage scaling (DVS) integrated circuits, sufficient timing and voltage margins are typically wasted, because it is difficult to anticipate the exact amount by which the voltage or frequency should be scaled. The on-chip timing monitoring method is effective for this problem. In this paper, an improved timing monitor circuit with a fast error comparator is designed to detect and correct timing errors, and then it is used in a DVS system on 65nm CMOS technology for deep DVS. Post-layout simulation results show that the monitor performs well in different process corners with a wide voltage range and wide temperature range. Compared with the non-DVS circuit supplied by a fixed 1.2V voltage, our timing monitor based DVS system can save, on average, 33.4% dynamic power in different corners at the expense of 22.9% increased area.

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This paper presents a novel page overwriting scheme for NAND flash memory. It provides significantly improved in-place page update with minimum hardware overhead. It does not require valid page copy for erase operation in order to modify data in a written page. Experimental results show 3.3 ∼ 47.5 times faster page update time with one overwrite allowance and 1.3 ∼ 18.7 with four overwrites allowance compared with conventional method.

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We demonstrate a simple and efficient optical coupler for vertical coupling between optical fibers and InP-based waveguides using a slant-etched mirror. The angle of the etched mirror can be controlled by using an aluminum jig with a beveled surface inserted under the substrate during RIE (reactive ion etching) of InP/InGaAsP. The off-chip coupler is fabricated simultaneously with a high-mesa waveguide with only one etching process. Coupling loss of 7.3dB between the tapered single-mode fibers is obtained within the wavelength of 1530-1570nm.

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