An efficient generic-point parallel scalar multiplication method is presented here where a new mapping technique is used with a modified version of the postcomputation-based method [6]. The results show that the proposed method outperforms that of the work in [6] when the number of consecutive requests is two or more. Furthermore, the results show that the proposed method is scalable for any number of parallel processors and performs better as the number of consecutive requests increases. This method consequently is very attractive for use in high-performance end servers that employ parallel elliptic curve processors.

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Complementary metal-oxide-semiconductor (CMOS) power cells for power amplifiers (PAs) were implemented and measured using a standard 0.35-µm CMOS process. An experimental analysis on the effect of substrate resistance on junction breakdown voltage is carried out to optimize the power-cell layout for CMOS PA applications. An optimized power-cell layout for improving junction breakdown voltage is proposed and verified through experiments in this work.

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Most commercially available Global Positioning Systems (GPS) do not provide location information that is sufficiently accurate to be used for practical location based services (LBS). Especially when there are high building structures nearby, GPS location measurements are known to be erroneous. In this paper, we present a computer vision based method for refining user’s two dimensional location and one-dimensional orientation starting from inaccurate GPS and digital compass measurements. Our method utilizes corner positions of buildings in the digital map and the building vertical edges in the captured images. Once calculated, refined user’s position and orientation can be used as an initial value for sensor-based tracking in accordance with user’s panning motion.

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In this letter, a multi-rank parallel accessing memory system based on 3D stacking and optical interconnection technologies is proposed. This proposed memory system can be a promising solution to future many-core system’s memory accessing bottleneck. Simulation results show that the proposed memory system yields the latency reduction of transactions and enhancement of bandwidth effectively. The worst case latency of 4 ranks and 8 ranks proposed memory system can be 1/3 and 1/5 that of the electronic bus-based ones. Bandwidth enhancement of 4 ranks and 8 ranks proposed memory system can be 3.5 times and 4 times higher than that of the traditional bus-based ones.

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This paper presents a low loss and high suppression monolithic inverse wavelet transform processor (MIWTP) using surface acoustic wave (SAW) devices. New functions for achieving the MIWTP have been derived. Its structure combines a withdrawal weighted single phase unidirectional transducer (SPUDT) with an apodized SPUDT. The experimental device is achieved with the aluminum electrode and the 128 degree rotated Y-cut lithium niobate (LiNbO₃) substrate. Measured results demonstrate the center frequency 68.1 MHz, the minimum insertion loss (IL) 5.4 dB, the 3-dB fractional bandwidth 1.3% and the sidelobe suppression over 40 dB.

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A self-correcting quadrature voltage controlled oscillator (QVCO) with phase correcting loop is proposed. It comprises the QVCO core and phase correcting loop, which corrects the quadrature phase error. Two LC VCOs, buffers, and phase shifters are coupled in circular configuration to achieve IQ symmetry. This paper introduces the idea of realizing QVCO with low phase noise and accurate quadrature phase by using the phase correcting loop. The simulation results based on the 65 nm CMOS process show that the self-correcting QVCO has a phase error less than 0.5° and 1 MHz offset phase noise of −120 dBc/Hz at 3.7 GHz with 49% tuning range.

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A novel technique is proposed to mitigate the SERs of combinational circuits by using the half guard band. During the layout placement, by sharing the guard band between physically adjacent cells, the soft error rates (SERs) can be effectively reduced with less performance penalty. Three-dimensional technology computer-aided design (TCAD) numerical simulation and circuit-level simulation are adopted to demonstrate the hardening performance.

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Based on a statistic algorithm, a novel all-digital controlled AGC loop for GNSS receiver chip is proposed in this paper. The algorithm achieves the AGC function as well as low cost by using the Gaussian white noise characteristic of GNSS signal. Gain settling procedure is optimized to at most two steps by accurate power estimation. The stability of the proposed feed-backward AGC loop is discussed, which is rarely involved in some similar GNSS chips. The AGC loop further composed of PGA is applied in a GNSS receiver chip and occupies an area of 0.21 mm². The measured settling time is less than 32 µs.

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The high resolution of the latest high-performance mobile display devices has resulted in an increase in the main frame buffer size and related bandwidth, and this is one of the main causes of a reduced battery life. As a means to solve this problem, one-dimensional line-based compression methods have been studies in order to be implemented in the limited chip design environment of the mobile display driver ICs. Conventional lossless compression techniques do not have a high compression ratio enough for complex images to ensure a sufficient power reduction. On the other hand, a wavelet-based 1D SPIHT method has been studied for use as a lossy-compression method with a high compression ratio while keeping the image quality. However, this method requires large hardware resources due to the performance for iterative calculations and sorting process. This paper proposes a novel wavelet-based lossy compression system that can achieve high compression and image quality while maintaining low complexity. The Frequency Adaptive Line Compression composed of 4-level DWT, horizontal predictive coding for the low-frequency regions, frequency selective zero-zone quantization for high-frequency regions, and frequency component entropy coding. Experimental results confirmed that the proposed technique could achieve a higher compression ratio than the one required of conventional lossless compression methods and could also be implemented with a significantly less complexity than the conventional SPIHT method at the same compression ratio.

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We developed a binocular three-dimensional range-sensor LSI with improved distance detection precision. The range-sensor LSI is fabricated by a 0.35 µm CMOS 1-poly 3-metal process, and the chip size is 4.10 × 3.90 mm². In stereovision, the detectable distance resolution is limited by the lateral number of pixels of the image sensors. However, improvement by increasing the number of pixels requires a large increase in the chip size. Therefore, we designed a method of improving the distance detection precision by slight slide coordination of pixel placement without increasing the lateral number of pixels. By an evaluation using the developed LSI, we confirmed that the distance detection precision of the range-sensor LSI was improved fourfold in comparison with that with normal pixel placement.

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We propose an optimal method for sizing and partitioning DRAM in the NVRAM based hybrid memory for a multicore system. Optimizing the size of DRAM in the hybrid memory is critical to capture the working sets of applications for performance improvement and reduce hardware cost. Given the QoS requirements of applications and architectural constraints, the proposed method can minimize the total DRAM size by determining optimal partitions using integer linear programming. It can be used to statically size the DRAM during a system design phase or dynamically partition the DRAM among applications under various runtime scenarios.

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This paper presents a circuit technique to enhance a timing margin between internal data and clock by enlarging an eye opening of the internal data in a unique current mode transceiver [1]. This technique compensates a systematic timing offset of the internal data, which is caused by unbalanced transmission current. The test-chip exhibits 0.1UI (Unit Interval) improvement of the internal data eye opening without significant power penalty, and achieves stable data communication through 50% longer transmission lines compared to the previous work [1].

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In this letter, a mathematical model in self-oscillating class-D audio amplifiers is proposed to describe the switching frequency variation as a fuction of the modulation depth. It is alleged in a very simple form which can be applied to any general structure adopting phase-shifting in the feedback filter, time delay of the loop, and the hysteresis window at the comparator. The main focus is set on the analysis of the phase-shifting filter which shows the least dependency on the modulation depth, which is not yet revealed.

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Recently, Manochehri et al. proposed a modified radix-2 Montgomery modular multiplication with a new recording method. In this letter, we present an improvement to their scheme that makes it simpler and faster. Manochehri et al.’s algorithm requires n + 2 iterations, whereas the proposed (non-pipelined) algorithm requires n + 2 iterations. Moreover, there is no need for post-processing to obtain the correct output, nor for a non-standard operation such as bitwise subtraction. The area/time complexity of our pipelined multiplier is reduced by approximately 24.36% compared to Manochehri et al.’s multiplier. The proposed architecture is simple, modular, and regular. Moreover, it exhibits low complexity and propagation delay. Accordingly, it is well suited for VLSI implementation.

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Three-dimensional (3D) topology of Network-On-Chip (NoC) has become a promising way to solve the problem of IP core scale expansions. It offers greater device integration and also can provide higher-bandwidth, lower-latency and lower-consumption inter-layer communication with the help of through-silicon-vias (TSVs). However, the low yield of TSV and high overhead become a primary problems. In order to obtain better performance at relatively lower cost, this letter proposes a new 3D topology based-on Partial Overlapped Clusters (POC) for NoC, which reduces the number of routers and TSVs by sharing part of vertical links flexibly. We evaluate the proposed topology through performance analysis and simulations, the results demonstrate it can reduce the overhead distinctly and provide satisfactory performance.

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As the density of transistors is increased, the processor suffers from not only high power consumption but also high temperature. We presented the system level thermal behavior analysis model (STAM) which uses minimum physical characteristics and activities for components of the processor to obtain thermal behaviors. STAM employs the state-machine-based model for a thermal transient response. The results show that STAM is more than three orders of magnitude faster than the existing temperature estimation tool, with about a 6% average error to find hotspots.

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Problems of electrostatic fields involving multiple conductors arise in various scientific fields. It is known that the relation between the electric potentials and the charges of multiple conductors can be expressed by a system of linear equations. However, the well-known system of equations holds true only when no other charge exists external to the conductors. In this paper, we derive an extended system of equations that is valid even if the conductors are immersed in electrostatic fields due to external charges.

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In this letter, a new simple circuitry LED driver with current reduction is proposed, realized and experimentally validated. The proposed circuit comprises with very few components intended for making a cost-effective and compact design while still shows a high performance. The circuit reduces non-conducting time of LEDs to enhance power factor (PF) and total harmonic distortion (THD). The flicker can also be relatively reduced. By using current limiter cells, lighting variation is eliminated with respect of the variation of AC input voltage. A worst case of a 4 W with only two LED-strings driver is implemented and tested by using a 1 um 650 V-BCDMOS high voltage process to verify advantageous characteristics of the suggested scheme. Experimental results demonstrate a PF of 0.97 with a THD of 24.62% and an efficiency of 87.1% at a 220 V AC supply.

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A fast and efficient automatic frequency calibration (AFC) technique suitable for high frequency PLLs is presented in this paper and a 10 GHz PLL using the proposed AFC circuit is designed in 65 nm CMOS technology. The fast AFC technique is achieved through a multi-phase clock sampling based algorithm which reduces comparison time of each calibration step to at least one reference cycle with small frequency resolution. A dual-mode frequency divider is proposed to save circuit cost for a high frequency multi-phase clock generator. The proposed divider generates 8-phase high frequency clock for the proposed AFC to reduce its calibration time. Simulation results demonstrate that the calibration time is less than 1.44 us for each output frequency. The proposed AFC circuit is competitive among published AFC techniques in calibration time, unit cycle frequency resolution, area cost and power dissipation.

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