This paper is dedicated to the coherent video modeling of pulsed Doppler radar seeker (PDRS) for the six degree of freedom (6-DOF) closed loop trajectory simulation, which provides an efficient tool to the design and evaluation of surface-to-air missile (SAM). The topics covered are waveforms consideration, radar antenna modeling, target scattering characteristics, receiver processing, signal processor design and filter mechanism in data processing. The augmented proportional navigation law is used to generate the acceleration demands, while the bank-to-turn control command to obtain the fin-angle demand and the 6-DOF missile motion solution can then be accomplished by using SAM’s aerodynamic characteristics. A typical air defense warfare scenario is designed to validate coherent video modeling as well as the 6-DOF closed loop trajectory simulation. The electronic countermeasures are also taken into account. Results show that VGPO has no direct effect on the angle tracking loop, just through guidance filter to affects the angular speed estimation astringency. It achieves only 2 towing cycle within a relatively short time of terminal guidance. The conclusion was consistent with the anechoic chamber measurements results, which proved that PDRS coherent video model is accurate for 6-DOF trajectory simulation. The paper provided an effective and practical solution for parameters designing and performance evaluation of tactical cruise missile.

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With more and more cores integrated in a single chip, three-dimensional network-on-chip (3D NoC) based on through-silicon-via (TSV) is a good way to deal with the problem of large network diameter. But if the number of cores increase to several hundreds or even thousands, the large number of TSV cannot be neglected any more due to the low yield and high overhead of TSV. Therefore, it is necessary to obtain a balance point between cost and performance. In this letter, we propose H-cluster that applies a hybrid vertical interconnect scheme. It minimizes the number of TSV by sharing vertical links through vertical routers. The simulation results shows that the H-cluster can improve the yield of many-cores chip and provide a better performance.

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This paper proposes a method to estimate the time delay and delay rate when forecast data is inaccurate, in the Very Long Baseline Interferometry (VLBI) signal processing for the radio science receiver (RSR). Firstly, we find out rough time delay and rough Doppler shift through cross-correlation chart by using multiple-correlation method to enhance the SNR, which is suitable for the low SNR situation. Secondly, the data is compensated to get linear phase-frequency curve of the cross-power spectrum and calculate the precise time delay and delay rate by iteration. The method is tested with both simulation data and real received data. Result shows the signal detection limitation is at SNR = −23 dB. The standard deviation fit error for the curve can be under 0.05 rad. The method effectively increases the data processing probability.

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A non common-node microwave chaotic Colpitts oscillator with enhanced negative resistance is introduced. Its negative resistance degradation caused by the Miller capacitance C_BC is compensated with an optimum inductor load. The fundamental frequency f₀ and bandwidth of this chaotic oscillation can be improved over a normal common-base or common-collector oscillators. This design also enables power consumption reduction in the oscillator.

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Phase change memory (PCM) is regarded as a powerful competitor for future non-volatile memory applications. However, a key drawback is its limited write endurance. This paper proposes a flexible block management method with data migration wear-leveling algorithm (FBDM). The proposed method divides blocks into two halves meanwhile blocks can be split and merged flexibly. Data migration wear-leveling algorithm has been presented to extend the life of PCM. We simulated our method using different traces and compare it with previous methods. Simulation results show that the proposed method outperforms comparison methods in terms of wear evenness and overhead reduction.

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In this paper, we propose a way to distribute the video analytics workload into both the CPU and GPU, with a performance prediction model including characteristics of feature extraction from the video stream data. That is, we estimate the total execution time of a CPU-GPU hybrid computing system with the performance prediction model, and determine the optimal workload ratio and how to use the CPU cores for the given workload. Based on experimental results, we confirm that our proposed method can improve the speedups of three typical workload distributions: CPU-only, GPU-only, or CPU-GPU hybrid computing with a 50:50 workload ratio.

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When implementing non-multiplier linear systems, delay-aware common subexpression elimination (DACSE) is a critical algorithm for optimizing the area efficiency under a given timing constraint. In this paper, we propose an optimized DACSE algorithm for the hardware implementation of binary-field linear transform (BFLT). In order to achieve the shortest critical path delay (CPD), the proposed algorithm uses fast-binary-tree structure to implement the BFLT circuit before sharing common subexpressions (CSs). However, as the delays of involved signals are different after sharing CSs, the delay-driven-binary-tree (DDBT) structure is adopted to further optimize the critical path of the BFLT logics. The CPD of the DDBT based circuit is evaluated for each case with an eliminated CS, and the CS elimination will be abandoned if the case cannot meet the given timing constraint. Moreover, the proposed algorithm provides all of the design trade-offs, from the shortest feasible CPD to the smallest area, to designers, offering them the maximum design space. Experiments are carried out to verify the proposed algorithm and the results show that the proposed DACSE is more efficient in area reduction than the previous works, especially under a stringent timing constraint.

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Researchers have proposed several schemes with hybrid cache architecture (HCA) which contains both SRAM cells and non-volatile memory (NVM) cells to overcome the drawbacks of NVM. The existing HCA schemes try to place a write intensive block into an SRAM way when a cache miss occurs. The cache replacement policy increases the write counts of NVM when the number of write intensive blocks are small. To solve this problem, we propose an adaptive replacement policy for hybrid cache architecture to adjust the cache replacement policy based on the write intensity for victim selection. The simulation results show that the proposed mechanism reduces the write counts of NVM by 21.2% on average compared that conventional replacement policy is used.

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This paper proposes a jitter suppression technique for a high-speed interface macro by decreasing the disturbance onto a power node of the macro. The power node fluctuates in accordance with the output data pattern from the macro. Namely, it becomes lower at the dense data pattern and returns near to an initial value at the sparse data pattern. This fluctuation causes the jitter and deteriorates the data eye on the output node. The proposed scheme relaxes the dense and sparse pattern dependency by decreasing the fluctuation. Simulation results show a significant suppression of i) the power node fluctuation from 20 mV to 8 mV, and ii) the jitter from 160 ps to 60 ps on the data eye. Clear data eye openings were obtained at various data rates on actual measurements.

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Relay technology is necessary for Power Line Carrier communication because of the harsh characteristics of the power line channel, including time-variance, strong noise and high attenuation. The Ant Colony Algorithm is a promising approach for implementing relay technology. However, the execution time for the conventional Ant Colony Algorithm is very long. This paper provides a novel approach to speed up the search process using a database together with Dijkstra’s algorithm. The experimental results show that the new algorithm can decrease the convergence time significantly in most types of topologies. In addition, robustness and invulnerability properties of the algorithm are also improved.

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A compact two-way planar Wilkinson power divider with dimensions of over 40 mm × 28 mm × 0.8 mm operating at L-band is presented. By using two comb-like symmetric defected ground structures (DGS), the divider is reduced by about 50% in size. The measured results demonstrate that the insertion loss is less than 3.2 dB, the input return loss is smaller than −15 dB from 1.3 to 1.7 GHz while the isolation is larger than 20 dB.

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In this paper, we give modified version of interleaved Montgomery modular multiplication method for lattice-based cryptography. With the proposed algorithms, we improve the multiplication complexity and embed the conversion operation into the algorithm with almost free cost. We implement the proposed methods for the quotient ring (ℤ/qℤ)[x]/(xⁿ − 1) and (ℤ/pℤ)[x]/(xⁿ + 1) on the GPU (NVIDIA Quadro 600) using the CUDA platform. NTRUEncrypt is accelerated approximately 35% on the GPU by using the proposed method. We receive at least 19% improvement with the proposed method for the polynomial multiplication in (ℤ/pℤ)[x]/(xⁿ + 1), where n ∈ {1024, 2048, 4096}.

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A novel topology of Q (quality factor)-enhanced dynamically self-biasing Class-C VCO is proposed in this article. It introduces a bridging capacitor to enhance the quality factor of the oscillator. The enhancement of the quality factor suppresses the squegging phenomenon and the harmonic distortion, and thus improves the phase noise and oscillation stability. The prototype of the proposed circuit was fabricated in SMIC 0.18 µm CMOS process and the measurement results showed a low phase noise of −125 dBc/Hz@1 MHz from 3.331 GHz carrier with a total power consumption of 3.36 mW from a 1.2 V supply. The proposed work exhibited an excellent Figure of Merit (FoM) of −190 dBc/Hz.

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