This paper reviews near-infrared Ge photonic devices on Si towards photonic-electronic integrated circuits on a Si platform, which play a significant role in short-reach optical interconnects. In particular, applications of Ge epitaxial layers on Si to photodetectors, light emitters and optical modulators are described.

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Carrier-depletion Si Mach-Zehnder modulators incorporating lateral PN-junction phase shifters are reviewed in the lights of fundamental characteristics and applications to high-speed optical fiber transmission. Experimental reverse-bias characteristics are supported by numerical analysis with good agreement, implying that the Si modulators are fabricated precisely as designed. Numerical high-speed response proves that the phase shifter operates beyond 100-Gbaud symbol rate. Traveling-wave electrodes are characterized in S-parameter measurements to reveal LRC resonance as a limiting factor in high-speed modulation. High-speed optical-fiber transmission in on-off and phase-shift keying formats is demonstrated using the Si Mach-Zehnder modulators assembled in ceramic-based metal packages.

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This paper reviews recent progress in integrated multiport optical switch, fabricated on silicon-on-insulator wafers. Typical topologies of multiport switch and the element switches are first described. Then, we review pioneering studies of the integrated multiport switches. We also describe feasible improvements, some of which will better fit the switch to a real use in telecommunication and some to enlarge the port count.

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With a new phase-rotating phase locked loop (RPLL), a 5-Gbit/s quarter-rate clock and data recovery (CDR) circuit is presented in this brief. The RPLL employs a split-tuned architecture to decouple the tradeoff between RPLL bandwidth and power consumption. The uncertainty of phase interpolation due to the non-deterministic characteristics of the phase frequency detector (PFD) is eliminated by employing a PFD synchronizer (PFDS). Hence RPLL precisely performs seamless phase adjustment. The CDR, implemented in a digital 65 nm CMOS technology, shows 5.5-ps rms and 47.2-ps peak-to-peak jitter in the recovered clock and 10⁻¹² bit error rate while consuming 10.3 mW from a 1.2-V supply.

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This paper presents a real-time hardware accelerator for single image haze removal using dark channel prior and guided filter on a FPGA chip. Single image haze removal using dark channel prior and guided filter is one of the state-of-art algorithms recently proposed. However, its large quantity of calculation limits its real-time processing ability. So, in this paper, we design a hardware accelerator based on FPGA implementation for single image haze removal, which takes full advantage of the powerful parallel processing ability of the hardware and the parallelism of the algorithm. To be exactly, 1) the dark channel calculation part and the atmospheric light calculation part of the algorithm are modified to reduce the quantity of computation; 2) two pipelines are applied in the guided filtering to speed up the processing; 3) in addition, fast mean filtering technique is used to accelerate the mean filtering, which is the main calculation of the guided filter, by avoiding redundant computation. To the best of our knowledge, this paper is also the first FPGA design for single image haze removal using dark channel prior and guided filtering. The design can achieve 13.74 ms at 100 MHz when processing a 720 × 576 image, and gives almost the same results as that of original algorithm.

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A novel auxiliary-free zero crossing detection (ZCD) circuit is presented in this paper, which is especially suitable for step down non-isolated LED drivers operating in boundary conduction mode (BCM). Without extra auxiliary winding, the proposed method can fast and correctly detect zero inductor current information, which only requires an integrated NMOS power switch. The step down non-isolated LED driver with the proposed ZCD scheme has been implemented in CZ6H 0.35 um standard CMOS process, results show that the proposed ZCD scheme can always work properly regardless of the variation of line voltage and load condition.

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A memristor is regarded as a promising device for modeling synapses in the realization of artificial neural systems for its nanoscale size, analog storage properties, low energy and non-volatility. In this letter, an adaptive T-Model neural network based on CMOS/memristor hybrid design is proposed to perform the analog-to-digital conversion without oscillations. The circuit is composed of CMOS neurons and memristor synapses. The A/D converter (ADC) is trained by the least mean square (LMS) algorithm. The conductance of the memristors can be adjusted to convert input voltages with different ranges, which makes the ADC flexible. Using memristors as synapses in neuromorphic circuits can potentially offer high density.

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A C-element is a key storage cell for constructing asynchronous circuits often used for reliable applications. This brief introduces a soft-error tolerant transistor/magnetic-tunnel-junction (MTJ) hybrid non-volatile C-element. To exploit the MTJ devices that are hardly affected by particle strikes in asynchronous circuits, a self-disabled write circuit is proposed that can write data to the MTJ device, asynchronously. The MOS/MTJ hybrid C-element implemented under a 90 nm CMOS/100 nm MTJ technology is simulated using NS-SPICE (SPICE simulator) that handles both transistors and MTJ devices. The simulation results show that the proposed C-element properly operates under a particle strike that induces a charge amount of 50 fC. It is more robust than a triple-modular-redundancy (TMR)-based C-element under particle strikes. In addition, the proposed C-element can be power-gated because of the non-volatility of the MTJ device, reducing the standby current to 0.41% compared to the TMR-based C-element.

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In mesh-based many-core architectures, processor cores and memories reside in different locations (center, corner, edge, etc.), therefore memory accesses behave differently due to their different communication distances. The latency difference leads to unfair memory access and some memory accesses with very high latencies, degrading the system performance. However, improving one memory access’s latency can worsen the latency of another since memory accesses contend in the network. Therefore, the goal should focus on memory access fairness through balancing the latencies of memory accesses while ensuring a low average latency. In the paper, we address the goal by proposing to predict the round-trip latencies of memory access related packets and use the predicted round-trip latencies to prioritize the packets. The router supporting fair memory access is designed and its hardware cost is given. Experiments are carried out with a variety of network sizes and packet injection rates and prove that our approach outperforms the classic round-robin arbitration in terms of average latency and LSD. In the experiments, the maximum improvement of the average latency and the LSD are 16% and 48% respectively.

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Generally, the time delay of simulated pulses generated by inverse synthetic aperture radar (ISAR) moving target simulator (MTS) is changing discretely with time. In this case, there must be time delay errors between simulated pulses and real pulses reflected by real target. As a result, the coherence of the simulated pulses will be worsened and the ISAR image would be blurred due to the time delay errors. In order to solve the problem, a compensating technique consisting of two steps is proposed. Firstly, if the simulated pulse and the real pulse are located at different range cells, move the simulated pulse into the range cells at which the real pulse are located. Secondly, compensate the phase errors between simulated pulse and real pulse. After step two, at the efficient sampling time instants, the digital samples corresponding to the simulated pulse are equal to that constructed from the real pulse. So the radar will treat the simulated target as a real target. In other words, the coherence and the ISAR image quality of the simulated target are guaranteed. The simulation results demonstrate the efficiency of the proposed technique.

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Recent increases in the type and amount of multimedia data has required a versatile device enough to play various data. Especially a variety of lossless compression algorithms often causes large amount of redundant computations. In this paper, an application-specific instruction processor tailored to effectively process such coding algorithms is proposed. The functionality and performance of the processor has been verified by using it to run the H.264/AVC baseline profile encoder. The experimental results show that the proposed processor can save about 96% and 36% of the execution cycles of ARM Cortex-A9 and Intel i7 processors, respectively.

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A new input feedforward sigma-delta modulator architecture is presented for the design of low-voltage low-power high-precision oversampling analog-to-digital conversion. A half-sample delay is added in the input feedforward path in combination with multi-bit quantization to reduce integrator output swing and relax timing constraints in the feedback path. This results in substantial reduction of power dissipation in both analog and digital circuits in the modulator. The proposed implementation shows that no additional circuitry is needed to realize the added half-sample delay, thereby not introducing circuit nonidealities and eliminating power and area overhead. To verify the effectiveness of the architecture, a second-order sigma-delta modulator was designed and simulated using macro-models and 0.18-µm CMOS devices. It achieves a dynamic range of 96 dB for a signal bandwidth of 312.5 kHz at a 40-MHz sampling rate, which corresponds to an oversampling ratio of 64.

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This study examined the properties of the electric field penetration of a dual metallic wall with narrow slots when the plane wave is incident. Integral equations for aperture electric fields on slots were derived and solved by applying Galerkin’s method of moments (MoM). The numerical results showed that a high level of electric field penetration, which is known as transmission resonance, can be obtained for a small plate spacing and two slots with the resonant length when both slots have a slight offset in the slot width direction. The maximum transmission resonance occurred at a transverse slot offset of 0.07λ for a given plate spacing. In addition, the penetration electric field fluctuates with the spacing of the plate, and the fluctuation period is approximately 0.5λ. The experimental measurements are also presented to validate the theory.

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This paper describes several phase noise suppression techniques for X-band (8–12 GHz) frequency synthesizer design in 65 nm CMOS technologies. A low noise voltage generator for varactor DC biasing is proposed to minimize its contribution to VCO phase noise, which minimizes the out-of-band phase noise. A crystal oscillator with low noise biasing is proposed to prevent bias and supply noise from deteriorating its output phase noise, which improves the in-band phase noise. A frequency synthesizer prototype was implemented in 65 nm CMOS technology and generates 8.6–12.4 GHz output frequencies, with a measured phase noise performance of −90 dBc/Hz and −110 dBc/Hz at 10-kHz (in-band) and 1-MHz (out-of-band) frequency offset, respectively. The prototype draws 33 mA current from a 1.2 V power supply and the core circuit area is 0.2 mm². The performance comparison demonstrates the prototype achieves the best phase noise performance among all published frequency synthesizers in X-band or higher frequencies.

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A 1K-bit phase change random access memory (PCRAM) with improved periphery circuits for better reliable operations has been successfully developed in 130 nm CMOS technology. A flexible write driver is proposed to provide a novel continuous step-down pulses by studying programming strategies while a reliable read circuit is designed by investigating the special transition characteristics of PCRAM, leading to an effective write operation and a non-destructive read operation without any additional changes of the storage states. In addition, a large sense margin has been achieved and the read results corresponding well with the write operations, which demonstrate the influences of technology variations have been considerably decreased with the proposed periphery circuits.

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