This paper describes the design of a CMOS temperature sensor intended to compensate for the thermal effect of NAND Flash cells. The temperature sensor is mainly composed of a SENSOR part and COUNTER part. The SENSOR part generates a pulse (T_PTAT); its width is proportional to absolute temperature (PTAT). Futhermore, the clamped sensing scheme is used to eliminate the effects of temperature and process skew variation of sensing circuits. The COUNTER part converts T_PTAT to digital codes. The proposed temperature sensor consumes a 0.017 µJ/sample at a conversion rate of 313 K sample/sec.

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This paper presents a high speed SAR ADC with distributed comparators and shared preamplifiers. In contrast with the previous design, the sharing preamplifier technique avoids input range degradation and comparators’ offset calibration. Also, the paper proposes a self-locking dynamic comparator to maintain its high speed and high robustness. Moreover, it consumes less power than traditional single cross-coupling comparator. The ADC is fabricated in 0.13 µm CMOS technology to achieve a performance of 6-b resolution at 270-MSps rate. Its power consumption is 4.25 mW under a supply of 1.2 V. The measurement results shows the ADC achieves an ENOB of 5.65b with a low frequency input and 5.17b with a up-to-Nyquist frequency input. The FoM of the proposed ADC is 313-fJ/conversion step.

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This paper is committed to design and implement FPGA clock network with overall considerations of speed and power in circuit design perspective. Mixed structure MUX, programmable delay adjustment unit and power-down bit strategies are presented to optimize its latency, skew and power. This clock network is implemented with 65 nm process and applied to own-designed FPGA. Test results indicate 21.7% reduction in latency and 54.5% reduction in skew, compared to counterpart FPGA device, while maintaining lower power consumption.

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A method to extract the complex permittivity of a dielectric material in a PCB is presented. The recessed probe launch allows striplines to be measured without the need of via transitions that are subject to large process variations. After pad parasitics are de-embedded using the two-line method, the complex permittivity of the dielectric is calculated from 20 MHz to 5 GHz using closed-form equations. Internal inductance is taken into account to prevent overestimation of the permittivity at low frequency.

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Zero switching point effect for successive-approximation-register (SAR) analog-to-digital converters (ADCs) is analyzed in this paper. Central span switching procedures are presented based on shifting zero switching points of digital-to-analog converter (DAC) to improve the linearity of SAR ADC and reduce DAC energy. Several central span switching procedures modified from previous merged-capacitor-switching (MCS) and monotonic switching schemes are analyzed, which is central span MCS (CS-MCS) and central span monotonic (CS-MON). By splitting most-significant-bit (MSB) capacitors, CS-MCS and CS-MON have linearity error reduction by a fact of 2 and √2. The DAC switching energy is reduced by 92.2% and 84.4% relative to conventional SAR ADC. With V_cm applied as reference voltage at LSB conversion, the energy reduction can be increased to 96.1% and 92.17%. Moreover, with comparator input transistors split into two parts, the energy reduction of CS-MCS switching procedure can be 95.3% and 97.6% with V_cm reference at LSB conversion. These central span switching procedures are not sensitive to V_cm accuracy since it is the reference only at least-significant-bit (LSB) conversions.

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In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spurious-free dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm².

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Different from the conventional way to investigate the coupling between adjacent TSVs, we take the discharging path into consideration as the impedance of silicon substrate is actually finite. This paper first analyzes the discharging path which exists between the victim TSV and the silicon substrate, and then by transforming the tapped capacitor circuit into a RC parallel circuit for the discharging path, the frequency-dependent expressions of the parasitic elements in the discharging path are obtained. Furthermore, we vary the impedance of silicon substrate to evaluate the impact of discharging path on the coupling noise. Through simulations, it indicates that the coupling noise on the victim can be reduced significantly by lowering the impedance of discharging path.

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A novel energy-efficient switching method for variable resolution successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed switching scheme achieves switching energy inspired by the early reset merged capacitor switching algorithm (EMCS) and monotonic capacitor switching procedure. Besides, the dummy capacitors are used to further reduce power consumption and area. When sized for the same static linearity as the conventional SAR ADC, the proposed method enhances the efficiency of switching energy by 99.6% and reduces the total area by 93.75%. Furthermore, the proposed scheme can achieve a variable resolution for SAR ADCs.

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A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process-variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process-variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800 mV in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.

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Phase Change Random Access Memory (PCRAM) has several characteristics that make it a promising candidate for main memory. In this paper, the challenges involved in incorporating PCRAM into the main memory hierarchy of flash-based systems are explored, and a hybrid memory hierarchy consisting of PCRAM and DRAM for SSD is proposed. To reduce the write traffic of Flash, a buffer management scheme for the hybrid memory is implemented. The proposed scheme above is implemented on basis of Disksim platform. The simulation results indicate that the proposed buffer algorithm can decrease the number of random write and erase operations of the SSD and improve the average system response rate obviously.

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This paper proposes a memristor SPICE model using the Tukey window (or tapered cosine window) function. Compared with the previously proposed models based on the boundary function, the proposed model is resistant to numerical errors. From the SPICE result of a relaxation oscillator, we observe that the proposed model can be effectively used to minimise the effect of round-off errors.

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