Optical network technologies, such as circuit switching, wavelength division multiplex and silicon photonics, have been considered for high-performance computing (HPC) systems to achieve low communication latency, high link bandwidth and low power consumption. However, conventional HPC systems still use packet networks with electric switches. Only active optical cables for inter-cabinet long links are borrowed from optical network technologies. This paper firstly reviews the gap between the conventional HPC networks and feasible optical network technologies. We explain our pessimism that this gap will continue to exist by the beginning of the post-Moore era, i.e. 2025–2030. It secondly illustrates our research vision that HPC networks will be able to adopt optical circuit switching, possibly using free-space optics in the post-Moore era.

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With continuous increase in the off-chip bandwidth requirements, conventional interconnection methodologies are quickly becoming incapable of meeting the demand. Recent progress in silicon interposer and 3D integration technologies seek to alleviate some of these bottlenecks. This paper reviews the evolution of conventional interconnect methodologies and recent progress in platforms allowing high-bandwidth low-energy chip-to-chip communication.

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SiC power devices have high temperature operation capability compared to Si power devices. The thermal characteristics of packaged SiC devices are important for thermal management in high temperature range. This study investigates thermal characteristics of a packaged SiC device for high temperature operation. The transient and steady state thermal resistances of the packaged SiC SBDs are measured using JESD51-1 standard. In addition, the numerical thermal simulation of the packaged SiC SBDs using finite difference method (FDM) are carried out considering nonlinear thermal properties of package materials. In the current research, the thermal resistance of the packaged SiC SBD increases by about 10% in the temperature rise from 27°C to 250°C.

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A novel hybrid microstrip/slotline transversal bandpass filter (BPF) based on a dual-mode slotline resonator and a microstrip triple-mode resonator is proposed. Both dual-mode slotline resonator and triple mode microstrip resonator are achieved by loading a T-shaped stub to an open-loop resonator. Two resonators are set in transversal to acquire the size reduction of the filter and desired coupling between resonant modes. Based on the structure, a five-pole BPF with central frequencies of 2.75 GHz and 0.5 dB bandwidth of 28% is designed. Three transmission zeros are achieved in the stopband of the filter, improving the stopband characteristics of the filter. The filter is fabricated and measured. Good agreements between measured results and simulated results verify the proposed structure well.

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High Efficiency Video Coding (HEVC) is the newest video coding standard beyond H.264/AVC. To more efficiently compress image frames, variable block size DCT/IDCT (from 4 × 4 to 32 × 32) as well as 4 × 4 DST/IDST is employed by HEVC. In this paper, a novel area-efficient IDCT/IDST architecture for Ultra-High Definition (UHD) video applications is proposed. To reduce hardware cost and improve throughput efficiency, a novel resource sharing scheme, a template-based constant multiplication structure and a transpose buffer structure are adopted. Experimental results show that the proposed architecture can address 8K × 4K (7680 × 4320, 30 fps) video sequences at 390 MHz with at least a 39.5% gate count savings. Consequently, the proposed architecture offers a cost-efficient solution for future UHD applications.

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In this paper, a double balanced mixer based on a novel planar balun with the operating frequency from 3.1 GHz to 10.6 GHz is proposed. This microstrip-to-slotline transition balun can block IF and DC components effectively in a wide band. Also, in order to provide better isolation, a compact low pass filter is connected to the IF port. As the measured results show, the mixer exhibits the conversion loss less than 15 dB with the IF up to 100 MHz and port-to-port isolation better than 25 dB. The proposed mixer can be applied in the ultra-wideband transmission systems.

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The bidirectional shortest path problem has important applications in VLSI floor planning and other areas. We introduce a new algorithm to solve bidirectional shortest path problems using parallel architectures provided by general purpose computing on graphics processing units. The algorithm performs parallel searches from the source and sink using Dijkstra’s classic approach modified with pruning and early termination. We achieve substantial speedup over a parallel method that performs a single parallel search on the GPGPU from the source to all other nodes but early terminates when the shortest path to the specified target node is found. Experimental results demonstrate a speedup of nearly 2× over the parallel method that performs a parallel search from the source with early termination on the GPGPU.

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This paper presents a parametrized VLSI architecture for an n-state Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5 µm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70 K transistors. For a performance of 50 filter iterations/second, the chip requires a clock frequency of 200 KHz where a negligible power consumption of 1.1 mW is observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20 MHz.

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A new electronically tunable allpass filter (ETAF) realization using the composite Current Feedback Amplifier (CFA) and Multiplication Mode Current Conveyor (MMCC) building blocks is proposed. First order non-minimum phase function with electronically variable output phase is derived. Extension of the filter to a linear quadrature-VCO design is then implemented. Simulation test responses of all these functions are satisfactorily verified.

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A general mixed-radix FFT design for in-place strategy is derived and a low-complexity scheme for efficiently implementing mixed-radix FFTs is proposed. In this method, we develop an accumulator that can simply and practically generate addresses for the operands, as well as the twiddle factors. This approach extends the range of FFT size and reduces the hardware complexity of any non-power-of-two memory-based FFTs. Finally, the 3780-point FFT is taken an example to illustrate the validation of the proposed method.

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A 128 Kb HfO₂ Resistive Random Access Memory (ReRAM) chip is developed based on HHNEC 0.13 µm 1P8M CMOS process. ReRAM is suffering the write yield problem due to the tail-bit issues and large resistance variations at high temperature. In this paper a novel Double-Reference and Dynamic-Tracking Write (DR-DTW) scheme and a Dynamic read scheme are proposed to fix these issues. The experiment results show that the tail-bit issues are almost eliminated and the write yield is improved greatly compared with traditional write scheme.

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We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.

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We numerically analyzed the performance of a T-shaped combiner with metal-insulator-metal plasmonic waveguides. We showed that an extremely low combining loss can be realized over a wide infrared wavelength region. Moreover, the combining efficiency can be controlled between 0 and 1 by changing the phase difference between two input light sources, and it appears to be insensitive toward unequal powers of input light sources. Finally, we proposed a novel, optical 90° hybrid coupler with a modified T-shaped structure.

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A transmission trimming method for Si waveguides using phase change material (PCM) is proposed. We used a 3D-finite difference time domain (3D-FDTD) method to calculate the phase and the loss of light induced by the trimming structures. With five small square patches of PCM on the waveguide, transmission trimming up to 32 levels can be achieved. It was found that the crosstalk of a MZI type optical switch can be reduced when the splitting ratio of the first coupler is corrected using this method.

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A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator input-referred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.

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