This work presents a power efficient QRS detection processor with self-adjustable processing resolution. As reducing the resolution of electrocardiogram (ECG) data in certain degree has little effect on the detection accuracy but helps cut down the calculation power, a total of eight processing resolutions are supported in the processor, which can bring different levels of dynamic power reduction. The processing resolution is scaled adaptively based on the QRS detection result to achieve optimized energy efficiency and guarantee acceptable detection performance. The processor is implemented in SMIC 40 nm CMOS technology and has a total area of 5655 um². When tested on MIT-BIH arrhythmia database with 50 MHz operating frequency and 0.9 V voltage supply, its power consumption is 77.7 uW, which is reduced by 27.4% compared to the original processor, while the area is only increased by 6.7%. And it also achieves relatively high detection result, with an average sensitivity of 98.63% and positive prediction of 98.86%.

This paper presents an instrumentation amplifier for ECG signals, compared with the traditional three op amp ECG read instrumentation amplifier, the circuit overcomes the disadvantage of low common mode rejection ratio due to resistance mismatch of the three operational amplifier. At the same time, the circuit uses the inverting integral amplifier as an DC offset feedback circuit to eliminate the offset voltage at the input of the amplifier. This circuit implements the class-AB control circuit to achieve high linearity output. The circuit is compact with few peripheral components. The circuit is designed and implemented by using 0.18 um CMOS Technology. The circuit test results show that the circuit can eliminate the input offset voltage of the 140 mv. And has a DC gain of 40 dB and a common mode rejection ratio (CMRR) of 120 dB at the 2 V supply voltage. THD is −64 dB, and the total input reference noise is 0.78 µVrms, the power consumption is 121.6 µW, the bandwidth is 2 kHz.

This work describes a capacitive type touch sensor readout circuit using a current based capacitance-to-time converter with comparator threshold level self-adjustment. The proposed circuit generates an output pulse with duty-cycle corresponding to the panel capacitance variation using a simple switch control block, a current generator, and a comparator. This does not require additional amplifiers and passive capacitors/resistors. As a result, the proposed scheme can lead to small size and low power on-chip solution with fast detection time compared to conventional touch sensor readout circuits. Furthermore, due to the comparator threshold level self-adjustment, the readout circuit is less sensitive to component mismatch and process variations. The readout circuit is implemented using CMOS 0.35 µm technology with core area of 100 µm × 27 µm and power consumption of 52 µW, which can detect the touch panel capacitance ranging from 5 pF to 50 pF.

A novel proportional series combining transformer using for power amplifier (PA) is presented. Compared with balanced series combining structures, the high efficiency range is extended by sophisticated power adjusting and impedance tuning. As a proof-of-concept, a 2.5 V dual-channel PA with the proposed transformer was implemented in standard 0.18-µm CMOS process. The fabricated PA achieved a saturated output power (P_sat) of 28 dBm and a maximum linear output power (P_1-dB) of 26.8 dBm with the power added efficiency (PAE) of 33.5% and 31%, respectively. With power mode control, the high efficiency range exceeded 8.2 dB. The PA satisfied EVM requirements of LTE 2.3 GHz 20 MHz/64-QAM signal and WLAN 802.11g signal, respectively.

We propose a novel multilevel pre-equalizer using an analog FIR filter having multiple binary delay lines composed of CMOS inverters. The proposed pre-equalizer can decrease the required circuit scale of conventional analog FIR filters based on binary delay lines. The required number of multiplier circuits was halved by the proposed design scheme in the case of four-level pulse amplitude modulation (4-PAM). The performance was investigated using numerical simulation of a 20-Gb/s 4-PAM multimode fiber (MMF) transmission system. The proposed pre-equalizer successfully compensated the 4-PAM signals, improving the error vector magnitude (EVM) from 40% to 21%.

This paper presents a ring oscillator structure which combines meta-stable states with Fibonacci ring oscillators (FIRO) and Galois ring oscillators (GAROs). Based on the new structure, a true random number generator (TRNG) of 64 bit was created. This new TRNG was verified by FPGA platform with Altera Cyclone IV series chips, and its output has attainted NIST SP800-22 certification. The testing demonstrates that the proposed meta-stable random number generators improve randomness over traditional methodologies.

We propose a novel mode analysis method named the polarization-split segmented coherent detection (PSCD) method, which can obtain a full set of amplitudes, phases, and polarization states of guided modes including degenerate modes in few-mode fibers within the speed limit imposed by the response time of the electronics. The detailed calculation process of formulas for the complex amplitudes of the LP₀₁, LP₁₁^even, and LP₁₁^odd modes from the measured inter-frequency signals of the four elements of a quadrant photodetector is described. In addition, the calculation errors of the formulas for the LP modes as functions of the rotation of the quadrant photodetector and the offset of the beam from the local oscillator are evaluated by numerical simulation. From these error analyses, we derive formulas to compensate for the effect of the rotation of the quadrant photodetector and to reduce the error due to the offset of the beam from the local oscillator.

An improved method to approximate max^* operation with Taylor Series for Turbo decoder is presented. Multiple expansion points are adapted to improve the BER performance. The parameter δ is introduced to determine suitable expansion points. The simulation results show that the proposed method with three expansion points when δ is set to 0.025 has almost identical performance compared with ideal Log-MAP algorithm and outperforms both PWL method and the original Maclaurin series method. The architecture of proposed method is also presented for implementation. Compared with PWL methods, the proposed scheme has reduced computational complexity and is feasible for hardware implementation. Besides, the architecture of proposed method keeps identical for different number of expansion points.

A low power dissipation sigma-delta (ΣΔ) interface for closed-loop capacitive accelerometer is presented. In order to reduce the power consumption, the front-end circuit blocks work on a much lower frequency than the electronic ΣΔ modulator, and a cascode inverter with dynamic bias is used as an operational amplifier in electronic ΣΔ modulator, reducing the power dissipation greatly and enhancing the immunity to PVT variations. The measured results indicate that, the total power dissipation is 2.2 mW from a 3.3 V power supply. The noise floor of the accelerometer is 7.2 µg/Hz^1/2 in a closed-loop operation, and the achieved figure of merit (FOM, 8 pW/Hz) is better than the previously reported works.

In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).