We developed a new compact model for the program operation of 3D NAND Flash memories. A modified 1-D Poisson equation was proposed that shows better accuracy than the existing model by reflecting the spatial distribution of electrons trapped by the program operation. Under various conditions of program voltage (V_PGM) and program time (t_PGM), the threshold voltage shift (ΔV_t) was extracted by TCAD (Technology Computer-Aided Design) simulation, and we used this data to validate our new model. It also provides validity of the model for program operation in 3D NAND flash memory along with various TCAD analysis data.

A 25-Gb/s transimpedance amplifier (TIA) is proposed and realised in a 0.18-µm SiGe BiCMOS process. A series-peaking network and a shunt-peaking network are used to increase the bandwidth of the modified TIA. A gain boosting circuit is used to optimize the input-referred noise. The chip occupies an area of 0.8mm², and consumes 82mW from a 3.3-V supply. The TIA transimpedance gain is ∼ 4.5K ohms. Bite error rate tests indicate that the sensitivity of the fabricated TIA is -13dBm for a date rate of 25.78125-Gb/s (Bit error rate (BER)=10^-12, λ=1310nm, ER=4.2dB, and 0.8A/W PD responsivity).

This letter proposes a 2.4-GHz low power WSN RF front-end with high conversion gain and low noise figure. The proposed complementary series feedback low-noise amplifier (LNA) achieves high voltage gain and low NF with low power consumption. In the passive down-converter, a g_m-boosted TIA employing local g_m-boosted feedback structure is proposed to improve the power efficiency. Fabricated in TSMC 55-nm CMOS technology, the proposed front-end achieves a measured conversion gain of 38 dB, a noise figure of 2.75dB at 2.4 GHz with the power consumption of 2.9mW under 1V power supply voltage and the chip area of 0.63mm×0.43mm.

A broadband matching network used to provide a suitable load resistance for the MOSFET over a large frequency range is one of the keys to realize a broadband fully integrated CMOS power amplifier (PA). However, the broadband off-chip matching network will occupy large printed circuit board area and bring more parasitic effects. The broadband on-chip matching network suffers from large chip area. The paper presents a fully integrated matching network, which replaces the standard inductors (STIs) with the multilayer series inductors (MSIs), for expanding the bandwidth and reducing the chip size. The fully integrated matching network is applied in a broadband PA, which achieves a good performance in the measured 133% fractional bandwidth from 500 MHz to 2.5 GHz. The maximum power-added efficiency (PAE) achieves 42.5 % and the saturation output power reaches 24 dBm. The chip area is 0.4 mm² at TSMC 0.18 µm technology process. It draws 100 mA from 3.3 V supply voltage and the static power consumption is less than 0.3 W.