With the development of communication systems, the memory effects of mixers, defined as frequency dependence and asymmetry of intermodulation (IM) products, have become prominent. Conventional mixer models cannot describe the changing characteristics of mixers’ memory effects versus tone spacing. Thus, this study aims to analyse the characteristics of mixers’ memory effects instead of developing a high-accuracy model to characterise memory effects. IM3 product characteristics are described using simplified generalised frequency-response functions and a multi-box behavioural mixer model. These characteristics show that the lower and upper IM3 products have inverse trends compared to tone spacing, except for frequency dependence and asymmetry.

This paper presented a noniterative weighted least squares (WLS) design of digital finite impulse response (FIR) filters for canceling the aliasing errors caused by the non-ideality of analog mixers and filters in bandwidth interleaving digital-to-analog converter (BI-DAC). Taking a BI-DAC with M sub-DACs as an example, we firstly deduced the approximation error function. Then, based on this approximation error function, the optimum coefficients of all digital FIR filters were obtained by using the noniterative WLS method. Further, we deduced the computational complexity of our presented noniterative WLS design. Several design examples were given to verify the performance of our presented noniterative WLS design containing their effectiveness and computational. The simulation results showed that, by using our presented noniterative WLS design, the minimum distortion error was 0.021dB, and the maximum aliasing error was -67dB which satisfied the desired spurious free dynamic range (SFDR) in a 11-bit BI-DAC system. Finally, we compared the computational complexity among our presented noniterative WLS design and another three optimal designs, and satisfactory simulation results were obtained.

An aesthetic wideband dielectric resonator antenna (DRA) based on the Minkowski fractal slot is firstly presented. The proposed DRA consists of a glass dielectric resonator (DR) with the laser engraving pattern, the ground with the Minkowski fractal slot, the fork-shaped microstrip line, and the substrate. By employing the Minkowski fractal slot, the TE₁₁₁ mode of the DR and an additional hybrid mode are excited to realize the wideband characteristics. A parametric study is performed to analyze the wideband DRA performance. The simulated results show the hybrid mode and TE₁₁₁ mode can be controlled independently. To achieve the aesthetics of the DRA, a school badge is engraved inside the glass DR. Finally, the proposed DRA is fabricated and measured. A wide impedance bandwidth of 38.4% and the peak gain of 6.5dB for S₁₁ < -10dB are achieved.

A CMOS bandgap reference based on switched capacitor is proposed in this paper. Temperature compensation is adopted to achieve better temperature coefficient (TC). Two first order compensated reference voltages are combined to realize a new reference voltage with lower TC. Due to the switched capacitor operation, power and area of circuit are reduced. Simulation result shows that the bandgap reference achieves TC of 14.5ppm/°C from -40°C to 120°C. Bandgap reference output voltage is 235mV with a ripple voltage of 700μV.

An ultra wideband common-mode filter based on coupling multiple resonance points is proposed in the letter. The coupling multiple resonant points are realized by four compact defected ground structure (DGS) cells, of which both the ends are C-type DGS cells and the middle are H-type DGS cells. The structure and size of these DGS units are different, which leads to their different resonance points. Because of the close distance between DGS cells, coupling inductors are generated between them, which can be used for smoothing filtering. A coupled LC resonator equivalent circuit model is built to explain the filter’s working principle. The DGS-based filter with an area of 20mm × 12mm are implemented under the differential microstrip line. The simulated results shows the filter can achieves a wide 15-dB common-mode suppression of frequency range from 2.9 to 12.6GHz. Good agreement between full-wave simulation and measured results is observed.

In this letter, measured radiation patterns of a 4×4 digitally reconfigurable transmitarray are presented. It is possible to get beam steering and polarization conversion operation using the 4×4 digitally reconfigurable transmitarray. There is a total of four PIN diodes in each unit cell of the transmitarray. The polarization conversion operation is realized using the upper two PIN diodes and the beam steering operation is realized using the lower two PIN diodes. “State1” and “State2” are the biasing conditions of PIN diodes of the lower layer. “State3” and “State4” are the biasing conditions of the upper two PIN diodes. These states can be represented as “0” and “1”. By arranging “0” and “1” on the top and bottom layer of the transmitarray, beam steering, and polarization conversion operations can be obtained digitally. This type of transmitarray is useful for radars, satellites, and other types of communications applications.

Nowadays, many applications require multiple power supply voltages for various sub-functional modules, especially in consumer electronics. The single input dual-output (SIDO) converter contains less components is good scheme than adopt two single input single output (SISO) converters. However because of the outputs are coupled with same magnetic component, it would suffer cross regulation problem. This paper presents a cross regulation solution for the SIDO AC/DC converter. By the rectifier diode of upper output winding is replaced with a synchronous rectifier switch and the stacked design of two output windings. The energy of the two output windings can circulate with each other. Therefore cross regulation can be effectively improved. The operation principles, design procedure of the proposed solution are present and descripted. A prototype circuit was built to validate the feasibility of the proposed solution. The main advantages of proposed converter are implemented with low cost analog IC, the synchronous rectification has lower conduction loss, the stacked windings design have less total turns number and lower voltage stress for synchronous rectifier switch.

We report the effect of a thick nitride layer on transmission loss in GaN-on-3C-SiC/low resistivity Si (LR-Si). Microstrip lines of finite length and width with ground pads were fabricated on three GaN-on-3C-SiC/LR-Si epitaxial structures with varying nitride layer thicknesses of 3.2, 5.3, and 8.0µm. The loss performance of microstrip lines on different substrates was evaluated in the frequency range of 0.1 to 9GHz. The sample with 8.0µm thick nitride layer showed a minimal loss of 0.3dB/mm at 9GHz compared to the other samples. The evaluated data from electromagnetic (EM) simulation also confirmed a decreasing trend of loss with increasing nitride layer thickness. Temperature dependent loss evaluation also verified the above fact.

This paper presents a digital background technique that intentionally exploits multiple dithers to calibrate conversion errors caused by interstage gain error and nonlinearity in high speed pipelined analog-to-digital converters (ADCs). Two independent, zero-mean pseudo-random signals are injected into the multiplying digital-to-analog converter (MDAC) alternately to estimate these errors. Least mean square (LMS) algorithms are adopted to quickly locate and track the calibration parameters. Simulation results are presented for a 800 MSps 12-bit pipelined ADC in a 40nm CMOS technology, similar to that described by Murmann and Boser [1], Keane et al. [2] and Nan Sun [3] using low-gain amplifiers. With calibration, the signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.74dB and 43.61dB to 70.54dB and 89.8dB, respectively. The proposed calibration technique has the advantages of simple implementation, arbitrary amplitude pseudo-random signals, and no restriction on the input signal of the ADC.