This paper presents a novel compact and broadband filtering balun using N-shaped spoof surface plasmon polaritons (SSPPs). The N-shaped SSPP unit cell’s lateral size has a 48% reduction compared to the rectangle-shaped counterpart. The proposed filtering balun is constructed by periodically etching N-shaped and mode-matching SSPP unit cells into the slotline balun consisting of the microstrip-to-slotline transition structures. The combination of the N-shaped SSPP unit cells and slotline balun realize the compactness and the broadband bandpass filtering response. Moreover, we can individually adjust the passband’s lower and upper cut-off frequencies. Due to the larger phase constant of the N-shaped SSPP unit cell, the field-confined ability of the proposed filtering balun is enhanced. The proposed design is fabricated and measured. It has advantages in bandwidth, stopband performance, size, and degree of design freedom compared with existing SSPP filtering baluns.

With the development of storage technology, NAND Flash’s reliability becomes more serious. The bit-flipping schemes and low-density parity-check (LDPC) codes are two effective methods to solve this problem. Motivated by error characteristics of NAND Flash and flag bits added by the bit-flipping scheme, an enhanced LLR optimization algorithm of LDPC is proposed based on the prediction of the threshold voltage state error rate (VSER) by flag bits. Compared with the conventional scheme, the proposed algorithm extends the data retention time to 25.44 times. The decoding iterations of LDPC are reduced by up to 87.74%.

Transcatheter renal denervation (RDN) has emerged as a novel treatment option to lower blood pressure (BP) by ablating the renal nerve. However, inconsistent results of failing to reduce BP were reported, primarily due to the inability to confirm ablation temperature at the treatment area. In order to address this, we proposed a microwave balloon catheter with a hybrid machine learning (ML) algorithm to achieve a deeper ablation and predict the temperature. Through an in silico evaluation using a human body model TARO, the proposed method achieved 1.5°C difference compared to simulation using TARO, showing the proposed ML method capability.

In-situ timing monitor is widely used in the adaptive voltage scaling (AVS) system to eliminate the excessive design margin preserved for PVT variation. However, most of them suffer from the short-path (SP) issue where SPs must be padded to exceed the speculation window, incurring significant area overhead. A new in-situ timing monitor based on timing-error prediction is proposed in this paper, which can monitor the timing of the circuit across a wide voltage range. The SP issue is resolved by an SP isolation unit, and the speculation window is carefully determined to guarantee accurate timing-error prediction. A lightweight 13-T transition detector (TD) is designed to detect timing violations of critical paths. Furthermore, the proposed method is APR-friendly to EDA tools. All the proposed techniques are implemented in a CORDIC chip for demonstration targeting the SMIC 55nm CMOS process. Results show that the whole design achieves up to 53.2% energy saving with 6.1% area overhead as compared to the typical margined baseline circuit.

Traditional von Neumann architecture bottlenecks such as the “memory wall” limit artificial intelligence (AI) development, and in-memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.

For multi-input piezoelectric energy harvesting, the issue of energy backflow between multiple Piezoelectric Transducer (PTZ) cause energy loss. Hence, an Isolated Active Rectifier (IAR) is proposed in this paper to address the problem. Based on the characteristic of energy isolation, the Multi-Input Synchronous Electric Charge Extraction Circuit (MI-SECE) with IAR can harvest energy from multiple PZTs with the arbitrary phase difference. The peak overall power conversion efficiency can reach up to 85.5%.

The balance between computational performance and power consumption is a key constraint in computing systems, with integrated circuit technology posing a bottleneck. Approximate computation can trade off accuracy for performance or power improvement in error-tolerant scenarios. Division, with high computational demands and latency, is a bottleneck for computational efficiency. We propose a quadratic interpolation approximate divider (QIAD) based on multiplicative division, which has superior statistical performance. The design is simulated and synthesized at TSMC 65nm process and tested on image color quantization, showing the best quantization effect using evaluation indicators such as PSNR, MSE, and SSIM.