With the development of GaN HEMTs, solid state power amplifiers are hopeful to replace the vacuum tube power amplifiers in more and more areas. However, the working voltage and power density of GaN HEMTs are still very low. Transistor stacking is a promising solution to ameliorate this problem. In this letter, we combine a unique high-voltage 0.25μm GaN-on-SiC technology and stacking topology together and build a high-voltage high-power-density high-gain GaN stacked HEMTs. Our stacked device combines two 20×120μm GaN HEMTs connected in serial to work at 140V. The output power and gain of the stacked device are 45.6dBm and 17dB, respectively, at 3GHz and 100μs pulse width/10% duty cycle. The power density reaches about 15W/mm, increased by about 41% compared with state-of-the-art stacked devices. To the author’s best knowledge, this is the highest power density and highest working voltage among microwave stacked transistors.

Due to the battery-life and practicality considerations, realizing only constant current (CC) or constant voltage (CV) output for a single load in a wireless charging system is not attractive. This paper proposes a compact inductive power transfer (IPT) system for multiple-load applications with automatic switching from CC to CV charging, based on transmitter-repeater-receivers coupler. The simplified equivalent circuit of the proposed coupler is established through circuit analysis. Based on this, the constant output characteristics and transmission efficiency are theoretically clarified. The safety and reliability of the system are assessed. The proposed system can achieve CC and CV switching for multiple loads, zero phase angle operation, and fixed operating frequency, which can improve the efficiency. Additionally, the communication between the transmitter side and the receiver side is not needed in the proposed system as well as complex control strategies. An experimental prototype with two loads is established and tested. Experimental results show that the output characteristics of each receiver remain almost unchanged when other receiver is removed or added. The maximum measured efficiency is 89.56% with a single load and 93.66% with two loads.

The present study proposes a frequency-dependent subcell technique for modeling Graphene thin sheet layers in the finite-difference time-domain method (FDTD). By employing the integral form of the Maxwell-Ampere equation, update equations are derived to accurately simulate electric fields within each subcell containing a Graphene thin layer. This innovative approach significantly reduces computational time and memory requirements. To validate its effectiveness, a numerical example is conducted to investigate wave propagation through a graphene thin layer.

This paper proposes a design for even-order variable fractional delay (VFD) finite impulse response (FIR) filters based on pivot element weighting iterative (PEWI) algorithm. Initially, a mathematical model is established for even-order VFD FIR filters to derive the actual variable frequency response (VFR). This VFR is then employed to calculate the error between the actual and ideal VFRs, which is decomposed into real and imaginary components. The design aims to minimize these errors, inherently involving the solution of ill-conditioned system of linear equations. The PEWI algorithm is designed to address these equations, thereby minimizing the real and imaginary VFR errors to determine the optimal coefficients for even-order VFD FIR filters. Comparative examples with linear programming (LP) and second-order cone programming (SOCP) methods demonstrate the enhanced effectiveness and the reduced computational complexity of our PEWI-based design over LP and SOCP.

The instantaneous output power of a dc pulsed power supply (DPPS) pulsates, resulting in the generation of low-frequency harmonic current (LFHC) in a front-end dc-dc converter. To suppress the LFHC and improve the dynamic performance of the front-end dc-dc converter, an improved active disturbance rejection control (ADRC) is proposed, taking into account the closed-loop output impedance. A moving average filter (MAF) and a phase-leading network (PN) are embedded in the forward path of the ADRC. The low gain characteristics of the MAF at the pulse repetition frequency (f_pr) and its integer multiples are utilized to effectively suppress the propagation of the LFHC. The addition of a PN allows the voltage-loop cutoff frequency to exceed f_pr, thereby significantly improving the load transient response of the system. Furthermore, a closed-loop parameter design method based on frequency response analysis is introduced. Finally, an 800W (average)/2kW (peak) DPPS was fabricated and tested, and the experimental results verified the effectiveness of the proposed control strategy.

A hybrid multi-objective differential evolution algorithm based on decomposition with a chain local search strategy (HMODEA/D-CLS) is proposed for electromagnetic (EM) optimization in microwave filter design. This algorithm usesthe individual selection based on diversity and the chain local search strategy to approach a local extreme point swiftly. The adaptive allocation strategy of computing resources is used to calculate the time for global optimization. Additionally, aone-dimensional convolutional autoencoder (1D-CAE) as a surrogate model to accelerate the design process.A wideband bandpass filter is designed to verify the algorithm. Compared to the MOEA/D algorithm, the proposed algorithm improves optimization time by approximately sevenfold.

A high-order (HO) perfectly matched layer (PML) implementation algorithm based on the Runge-Kutta method is proposed for truncating the computational domain in the finite-difference time-domain (FDTD) method. We name this algorithm the RK-HO-PML. This algorithm introduces the Runge-Kutta method with second-order accuracy to solve each auxiliary variable in the HO-PML for the first time. It avoids complex operations such as the Z-transform, the recursive convolution, and the cascade solution, making it easy to understand and implement. Two typical numerical examples are provided to demonstrate the RK-HO-PML algorithm. The results show that the RK-HO-PML significantly outperforms its low-order version, namely the RK-LO-PML, and slightly exceeds other HO-PML algorithms.

Digital Single Event Transients (DSETs) induced by high-energy ion hit cause system errors in digital devices. The occurrence frequency of the error depends on the transient pulse width. In addition, as represented by the Propagating-Induced Pulse Broadening (PIPB), the pulse width increases or decreases depending on combinational logic circuit configuration in which the pulse propagates. We propose a new technique (not a simulation) that enables investigating the pulse width modulation in complex circuits, e.g., an adder circuit, without additional test circuits. The proposed technique observed the pulse width broadening of 190 ps with a confidence interval of ±94ps in an 8-bit ripple carry adder fabricated by 0.18µm bulk CMOS technology.

Statistical analysis for the yield of large-scale circuits is quite difficult due to expensive simulations, especially for the memory circuits with high sigma requirement (e.g., SRAM). In this paper, we developed an efficient sparse additive model to substitute simulations. To fit high sigma region accurately, the modeling center is moved to near failure boundary searched by scaling the shape of sampling function. To solve the model efficiently, the process variables are grouped by standard cells so that the model can be solved by our developed blockwise greedy algorithm. The experiments on the 28nm memory circuits validate that our method achieves high accuracy and efficiency compared with other state-of-art works.

This letter presents a RF switch in a 130nm COMS process for N77 1T2R mode application. The switch optimizes the number of branches with a unique asymmetrical structure and features a novel switchable terminal design that improve the deterioration of the antenna port’s return loss caused by the open circuit when the switch is completely turned off. It also incorporates body-gate negative biasing to improve the linearity. The measured insertion loss is less than 1dB and return loss is greater than 18dB for the main channels at 3.75GHz, with isolation no less than 33dB. The P_0.1dB reaches 39dBm while the second-harmonic is -87dBc and the third-harmonic is -96dBc when the input power is 30dBm at 3.75GHz.

Mesochronous is widely adopted due to its abilities to simplify timing closure and enhance modularity. Increasingly, various application scenarios demand improved performance, requiring higher levels of real-time capability and determinism. There is a relationship where clock frequency is the same, and phase is fixed but unknown between mesochronous modules. Cross-clock domain issues must be considered when transferring data between two modules. In this brief, we introduce a novel mesochronous dual-clock first-input-first-output (FIFO) buffer. This design adopts suitable transmission technologies based on signal characteristics to address cross-clock domain issues effectively. Moreover, it adopts a tightly coupled strategy for data read and write, which significantly minimizes fluctuations in the time from data writing to reading and simplifies the overall system design. Compared to existing dual-clock asynchronous FIFOs, the proposed design boasts the advantages of low resource costs, shallow buffer depth, and high determinism in forward latency. Extensive analyses and actual system tests have been conducted on it, validating its effectiveness.

In this paper, an ultra-short wave environmental energy harvesting system consisting of a rectifier antenna and a voltage regulator chip is proposed to collect the RF energy at 100-300MHz with an input power of 15-25dBm to obtain stabilized voltage that can be used for charging battery. The size of the rectifier antenna is 274.86mm × 144.38mm, which is miniaturized in the ultra-short wave band by introducing the fourth-order Hilbert fractal structure and the slow-wave cross-finger structure, and it has seven resonance frequency points with S₁₁<-10dB. The rectifier circuit adopts a third-order voltage doubling rectifier circuit to rectify and filter the RF energy in the range of 15-25dBm. The voltage regulator chip consists of three modules: pre-regulator, bandgap voltage reference (BGR) and low-dropout regulator (LDO). The pre-regulator structure reduces the wide range voltage of 3.3-21V obtained after rectification to 3.3-5.1V, and then a stabilized output voltage of 3.27V is achieved through LDO. Experimental results show that the system has great potential for harvesting ultra-short wave RF energy in the environment.