A new low-cost configurable P-2APUF structure is proposed in this paper to solve the predictability problem of Physical Unclonable Functions (PUFs) under machine learning attacks. The structure is composed of Arbitrated PUF (APUF) and Pseudorandom generator (PRNG). By changing the configuration of incentive bits, one APUF generates two different PUF structures, and combines incentive expansion mechanism and output obfuscation mechanism to achieve anti modeling attacks. FPGA experimental results show that the circuit is predicted to be about 52.16% effective against modeling attacks with 20,000 sample sizes using 128 LUTs (look-up tables) and 5 DFFs (D-type flip-flops), and up to 94.31% reliable under different noise environments. Therefore, the P-2APUF structure maintains low overhead and high reliability while achieving resistance to modeling attacks, providing a reliable and secure solution for device authentication and key generation.

With the widespread application of the global system for mobile communications (GSM), the impact of GSM on human health has become a current research issue. Frequency-selective surface (FSS) shielding is a significant method to address such interference. In this article, a novel geometric design for FSS was proposed to block GSM signals and wireless communication (Wi-Fi) signals, with a cell size of 0.072λ₀×0.072λ₀, a transparency of 70%, and an incidence angle of up to 80° in transverse electric (TE) and transverse magnetic (TM). In addition, a novel methodology with a miniaturized design was introduced to reduce the graphic density and improve the transparency of the FSS. The relationship between the geometric element parameters and the resonant frequency was analyzed and optimized using surface currents and equivalent circuit models. Then, a prototype of the FSS was fabricated, achieving a satisfied shielding effect in a microwave darkroom. This design provided better miniaturization, transparency, and frequency stability than previous designs.

This paper presents an adaptive biased NMOS LDO which contains an adaptively biased pulse-frequency-modulated (PFM) charge pump to improve efficiency. Compared with conventional architecture, the ground current of the proposed LDO is halved under 3mA load current by regulating the charge pump frequency based on the sensed output current. In addition, the power supply rejection is also improved to 66dB@10kHz due to the relatively stable charge pumped. The proposed LDO achieved 99.995% current efficiency under 1A load. The proposed LDO was built with 0.18µm BCD technology. The simulated line and load regulations were 0.199mV/V and 53nV/mA, respectively.

This paper presents a fully synthesizable spread spectrum clock generator (SSCG) based on a fractional-N Digital PLL (DPLL). The designed SSCG adds a triangular digital signal to the frequency control word (FCW) to down-spread the frequency of the clock signal and reduce its electromagnetic interference (EMI) to near signals. Because of the linear frequency modulation of the triangular signal, the designed DPLL can be configured to operate in a Type-III mode to track the frequency variation more accurately than a Type-II setting. A proof-of-concept prototype was built using a 65nm CMOS technology. The measured EMI reduction because of the SSCG operation was 22.0dB. The designed SSCG is based on a fractional-N DPLL, which gives a 1.0GHz signal from a 100MHz reference frequency and consumes 4.83mW and 3.1mW from a 1.2V DC supply in the fractional and integer mode of operation, respectively. The measured rms jitter of the designed prototype was 3.95ps and 2.1ps in the fractional and integer modes of operation, respectively. The core area of the developed prototype is 0.1mm².

This paper presents a novel feedback structure for a multi-octave power amplifier (PA). The topological prototype of this structure is the Bartworth low-pass filter (LPF). The passband of the LPF is designed to compensate the PA at the low performance band, enabling the bandwidth (BW) of the PA to be smoothly broadened. To verify the proposed theory, a PA is designed and fabricated using a 10-W GaN HEMT. Measurement results show that the PA operates over a multi-octave band from 0.5-3.0GHz, corresponding to a fractional bandwidth of 142.8%. This PA provides a drain efficiency (DE) of 60.2-80.2% and an output power (Pout) of 39.2-42.1dBm over the operating band.

This paper proposes a leading angle flux-weakening speed regulation strategy based on sliding mode control for surface-mounted permanent magnet synchronous motorized spindle (PMSMS). The traditional flux-weakening control strategy suffers from problems such as low-speed jitter and a narrow range of speed control. To address this issue, the proposed strategy uses a sliding mode controller instead of a PI controller to adjust the speed error and eliminate poor control performance. The sliding mode controller introduces an integral term and uses the hyperbolic tangent function to make the sliding mode switch smoother, reducing the “jitter” phenomenon and improving system control quality. The strategy also uses a three closed-loop control of the speed, current, and voltage, where the motor terminal voltage and the DC side voltage form the voltage control loop, producing the motor current field. Experimental results show that the leading angle flux-weakening speed regulating strategy based on sliding mode control has better dynamic characteristics at higher speed ranges. It improves the spindle starting process efficiency by nearly 60%, and suppresses stator current oscillation and torque ripple. Moreover, the stator current of the direct axis and the intersecting axis is significantly smaller than that of the conventional control strategy during steady speed, while the transition process is smoother, which is more conducive to subsequent high-precision machining processes. The proposed strategy improves the speed regulating performance of the permanent magnet synchronous motorized spindle, realizing high-quality drive and operation of the spindle unit.

This paper presents a broadband fully differential amplifier using a 0.8-μm InP DHBT process, exhibiting a bandwidth exceeding 8GHz from DC and achieves a differential gain of 14.56dB, occupying 0.78mm × 0.7mm with all pads involved and consuming only 375mW with a -5V power supply. The core of the design leverages an operational amplifier with Cherry-Hooper architecture, incorporating global shunt-shunt feedback to ensure high gain linearity across the bandwidth. Notably, the -1dB bandwidth of this circuit extends up to 5GHz. Additionally, the design is entirely devoid of inductors, resulting in a consistent gain profile without any significant gain peaking.

Inter-turn short circuit (ITSC) is a common fault in permanent synchronous motor (PMSM). To enhance the ability of fault detection and location in PMSM, a diagnosis method based on square of negative sequence current vector modulus is proposed. First, we establish mathematical models of PMSM under healthy and faulty condition. Second, the amplitude and phase angle of second harmonic component in the square of negative sequence current vector modulus are analyzed theoretically based on superposition theorem and symmetric component method. Finally, the experiment is carried out on an 8-pole, 36-slot prototype, which verifies the effectiveness and accuracy of theory.

This paper introduces a novel hardware acceleration circuit designed to address the storage address offset issue in Convolutional Neural Networks (CNNs) during the feature map padding process. Traditional CPU-based padding and data transfer methods are computationally intensive and lead to high latency and power consumption, especially on edge devices. Our solution automates and integrates feature map padding and transfer. This significantly reduces DRAM access and improves the speed of transferring feature maps between DRAM and on-chip SRAM. The proposed circuit, tested on the ZCU102 development board using YOLOv4-tiny’s convolutional layers, demonstrates a speedup of over 20 times compared to CPU-based methods and more than 4 times compared to CPU with DMA.

A demodulation circuit for Hall sensor applications, which cancels offset by employing sequential voltage iterations across stack capacitors, is proposed in this paper. The circuit utilizes stack capacitors and a summing amplifier to perform offset sampling and cancellation. As there is no holding after sampling, the chopping ripple is effectively suppressed, thereby alleviating the use of area-consuming low pass filter (LPF). Under 0.18µm process, the Hall sensor with proposed stack capacitor offset cancellation (SCOC) demodulation circuit achieves higher bandwidth, better signal continuity, lower ripple and lower residual offset compared with two common offset cancellation (OC) circuits. The simulated ripple and residual offset are 38.1µT and 4.1µT respectively.