In this work, a dynamic variable duty-cycle control strategy for switched reluctance motor based on interval partitioning and current error analysis is studied. This method reduces current pulsation by dynamically adjusting the voltage of the conducting phase winding. Firstly, the voltage across the winding is adjusted by changing the duty cycle. Secondly, the intervals are divided based on the linear model of the inductance, and at the same time, the optimal duty cycle combinations are selected for different intervals and speeds according to the different current errors, effectively solving the defect of large current pulsation in the current chopping control of the switched reluctance motor. Finally, the proposed method was verified by simulation and experiments on a 12/8 switched reluctance motor, confirming that the method proposed in this paper can effectively suppress the peak value and pulsation of the current.

This paper discusses the effect of mechanical installation errors on the c results of capacitive angle sensor by COMSOL Multiphysics software; the angle was calculated using sines and cosines with capacitance value of the capacitive angle sensor. First, based on the principle of the sensor structure, the formula is derived which is petal-shaped in polar coordinates, and set the electrical parameters and rotation angles to realize the model simulation. Secondly, due to the installation errors which are easy to occur in real life, the simulation results are obtained by tilting and moving the model body to imitating the installation error in different cases. Finally, the results of installation errors in different initial situations are further analyzed and compared, including different tilt angles and horizontal movement distances respectively, and summarizing the impact of different installation errors on the measurement results.

This paper presents a fully-integrated dual-mode switched-capacitor (SC) DC-DC converter to supply always-on wake-up timer in biosensor systems. To balance chip area and conversion efficiency, optimal sizes of power switches, flying capacitor (C_fly) and output capacitor (C_out) in SC cell are determined through power loss analysis method. Power-on and self-powered modes (dual modes) under two voltage domains and an on-chip ultra-low-power (ULP) bias circuit are proposed to further improve the conversion efficiency. Furthermore, a hybrid self-biased current (HSBC) scheme is utilized to achieve low output voltage ripple. Implemented with a 40-nm CMOS process, this DC-DC converter can realize the voltage conversion from 1.8 V to 0.4 V. Measurement results show that the peak conversion efficiency reaches 75% at average load arriving 3 μA, while the voltage ripple is below 12 mV over 10 nA-5 μA load range.

This article presents a DC-DC converter designed for photovoltaic power conversion in biomedical implants. The design employs a differential topology for switching signal generation, enhancing signal robustness while reducing auxiliary circuit overhead. An input-supplied bootstrap circuit enables cold-start capability and prevents signal decay at low input voltage conditions. The circuit maintains optimal power conversion efficiency across a wide range of input conditions through oscillator tuning and charge pump reconfiguration. Implementation and simulation in 180 nm CMOS process demonstrate end-to-end power conversion efficiency of 50-86 % across an input power range of 1.6 nW-150 μW. The converter remains operational from 723 pW-500 μW with input voltages of 128-420 mV, while maintaining cold-start capability throughout this operating range.

The inherent open instruction set architecture of RISC-V processors, while promoting flexibility and customization, also renders them susceptible to Hardware Trojan (HT) attacks. Addressing this critical vulnerability is paramount for ensuring the security and integrity of modern computing systems. In this work, we present a novel real-time HT detection methodology for RISC-V processors by monitoring data and address path changes tied to core instructions and strategically leveraging pipeline node characteristics. It eliminates the need for a Golden Chip reference or extensive gate-level features. Upon detection, in-pipeline recovery is triggered. Validation on a three-stage RISC-V processor demonstrates that all tested HTs are reliably identified, with processor recovery completed within three clock cycles. Hardware implementations on FPGA and 40 nm CMOS technology substantiate rapid recovery and robust security protection.

To address power-sensitive neural network applications at the edge, computing-in-memory (CIM) with reduced data transfer costs has been proposed. The power and area overhead of traditional ADCs limits the efficiency of analog-based CIM. This paper proposes a CIM macro with a novel data-sensitive multi-slope (DSMS) voltage-time-digital converting (VTDC) ADC to efficiently perform multiply-and-accumulate (MAC) operations. The VTDC measures the bit line recharging time to reduce the need for high-cost ADCs. The DSMS technique adjusts the voltage-time slope based on input data to further optimize energy consumption and conversion time. The chunked array control (CAC) circuits facilitate faster weight updates. The CIM macro achieves an energy efficiency of 631 TOPS/W and an area efficiency of 8.4 TOPS/mm² for binary MAC operations. It exhibits less than 1.5% accuracy loss on the MNIST and CIFAR-10 datasets compared to the software baseline.