This paper presents a 600 V full integrated gate driver integrated circuit (IC) with a level shifter which is designed for the insulated gate bipolar transistor (IGBT). The chip integrates a low-power four-pulse level shifter, comprising a dynamic current generator with a logic mismatch detection circuit, a latch cell, and an advanced inverter. In the case of a logic level mismatch, the dynamic current generator generates a pulse current, thereby preventing the competition current that results from the simultaneous conduction of the pull-up and pull-down devices. The circuit enhances switching speed and significantly reduces dynamic power consumption. The level shifter employs fewer components, occupies a reduced silicon area, and features low-power consumption, rendering it highly suitable for low-power applications. The proposed low-power four-pulse level shifter has been successfully realized using 3 μm BCD technology. Experimental results indicate that under the conditions of a low input supply voltage of 3 V and a working voltage of 15 V, the delay is 6.574 ns for a 1 MHz input signal while maintaining low-power consumption.

This paper analyzes the common-mode interference conducted by the planar transformer in an isolated DC-DC converter and proposes a scheme for common-mode interference suppression. The scheme integrates the compensation capacitor for suppressing the common-mode current into the planar transformer, and its working principle is briefly explained in the paper. In addition, the scheme is verified by an active clamped forward converter. The application of this scheme in forward converter requires that the filter inductor on the secondary side be placed between the source of MOSFETs and the ground of secondary side, and it is necessary to add an inductor at the feedback terminal of the compensation loop, which needs to be coupled with the secondary filter inductor to ensure the normal driving of the MOSFETs. Finally, we made a prototype with an input voltage of 28 V and an output voltage of 5 V, and tested the common-mode interference of the prototype when using different planar transformers, which verified the feasibility of the scheme proposed in this paper.

This letter presents a 27-32 GHz compact phase shifter (PS) and attenuator (ATT) in 16-element phased-array for satellite communication (SATCOM) in 65-nm CMOS technology. Each element comprises a 5-bit switched-type attenuator (STA), a driver amplifier (DA), a 6-bit vector modulation phase shifter (VMPS) and a two-stage power amplifier (PA). STA occupies an area of only 60 μm × 100 μm, enabled by capacitive compensation technology. Furthermore, an extremely compact layout of the I/Q signal generation reduces the VMPS area to 140 μm × 225 μm.

An auxiliary gate driver for crosstalk suppression in the bridge-leg of eGaN power devices is proposed in this paper. Its essence is to use the negative voltage during the capacitor discharge process to realize positive crosstalk suppression and avoid worsening negative crosstalk voltage after capacitor discharge ends, which has the advantages of easy integration and requires no additional control. Experimental results verify that the proposed gate driver can decrease the positive crosstalk voltage by 2.48 V and improve the turn-off time by 35.71%. The proposed circuit can provide a basis for further improvement of eGaN gate drivers.

Design of multiband antennas supporting GPS L5, N77, and Wi-Fi 5G remains challenging. This paper proposes an aperture tuning method for multiband antennas that applies a filter circuit at the quarter wavelength of N77 radiator to achieve independent tuning for each band, and has the characteristics of simplicity, low cost, and miniaturization. This filter circuit exhibits different impedance characteristics in GPS L5/N77/Wi-Fi 5G. Furthermore, a band-pass filter is added between Wi-Fi 2.4G and Band 40 to decouple. Results based on a real smartphone show this design meet requirements of -6 dB impedance bandwidth, with isolation of 18.3 dB. The obvious advantages in terms of frequency band coverage, efficiency improvement, and isolation optimization make it highly compatible for modern smartphone applications that require high performance and compact integration.

The Advanced Encryption Standard (AES) is a fundamental cryptographic algorithm widely used to secure data in embedded systems, IoT devices, and cloud computing platforms. However, recent research on AES hardware accelerators face challenges in achieving high performance and hardware efficiency, particularly when supporting multiple modes and key sizes. To address these limitations, this paper proposes a hardware-efficient RISC-V accelerator with low-latency AES instruction extension (AES-RV), designed to enhance both processing speed and energy efficiency across various AES configurations. Specifically, AES-RV incorporates three key optimizations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with low-latency custom instructions, and system pipelining with a ping-pong memory transfer mechanism. The AES-RV accelerator is implemented and evaluated on a real-time Xilinx ZCU102 FPGA system-on-chip (SoC), utilizing 29,608 FFs, 32,483 LUTs, and 12 BRAMs. Performance comparisons against a baseline RISC-V implementation for multiple AES modes and key sizes demonstrate latency improvements ranging from 195.5 times to 255.97 times. Additionally, evaluations against powerful CPUs and GPUs in real-time AES executions reveal energy efficiency gains of 9.92 times to 453.04 times. Compared to state-of-the-art AES hardware accelerators, AES-RV achieves throughput improvements of 13.56 times to 33.52 times, energy efficiency enhancements of 2.36 times to 58.76 times, and area efficiency gains of 91.42 times to 638.8 times.

This paper presents a kind of novel deformed square coaxial resonator (DSCR) that exhibits a more compact size and maintains high unloaded (Q_u) factors. Specifically, compared with the graded dumbbell coaxial resonator (GDCR), the proposed resonator can achieve an 11% reduction in volume and an 11% increase in Q_u values. Furthermore, through reserving a small section surface, the proposed resonator can be applied to design inline mixed coupling filters with conventional metal coupling windows. The mixed coupling coefficients can be adjusted simply by changing the width of the coupling window. To validate the advantage, a four-pole inline mixed coupling filter was designed. For rapid demonstration, the 3D metal printing technology was adopted to print the filter. The printing tolerance is pretty good, and the measured results agreed well with the simulated results.

This paper proposed an optical diffractive deep neural network based on metasurfaces for efficient handwritten digit recognition tasks. The network achieves precise control of the light field by using the flexible phase modulation capability of Pancharatnam-Berry metasurface, thus constructing an all-optical diffractive neural network. Simulation results show that the proposed D2NN achieves over 90% classification accuracy for handwritten digits “0”, “1”, “2”, and “4” on blind test datasets. Additionally, the designed metasurface unit has a transmission efficiency as high as 95% at 1 THz, with digital images produced by metal masks being focused in designated areas after passing through the three-layer hidden layer of the metasurface. This study provides new insights into optical computing based on metasurfaces, offering potential application in machine vision, image processing, and real-time object recognition.

This paper proposes a dual-band RF switch in 40 nm CMOS with low insertion loss and high isolation for 5G millimeter wave. Body floating technology and transistor custom layout are adopted to reduce the insertion loss of the switch. Parallel resonant network and shunt-to-ground transistor are adopted to improve the isolation performance of the switch. By switching the inductor of the resonator to adjust the switch frequency band, the bandwidth of the switch is improved. The measured results show that the insertion loss in 22 GHz~45 GHz band is less than 1.6 dB, and that in 28 GHz is 0.9 dB. The isolation of 28 GHz and 39 GHz is 40 dB and 51 dB, respectively, and the isolation of the entire frequency band is greater than 25 dB. The return loss below 40 GHz is less than 10 dB, the chip size of the dual-band switch is 0.3×0.4 mm², and the core area is 0.05×0.1 mm².

The integration of third-party IP cores into IC designs significantly increases the risk of stealthy hardware Trojans (HTs). Existing detection approaches, based on functional testing, logic verification, or machine learning, often focus on individual gates and overlook the structural patterns across Trojan circuits. Moreover, they lack diagnostic capabilities and typically require manual inspection. This work presents TrojanHound, a hierarchical detection framework that unifies gate-level analysis and circuit-level diagnosis. It leverages a graph neural network with adaptive neighborhood aggregation to identify suspicious nodes, merges related components into candidate subcircuits using subgraph fusion, and verifies HT presence through topology-aware analysis based on betweenness centrality. Experiments on 14 TrustHub benchmarks show that TrojanHound achieves a 95.64% true positive rate and a 97.44% F1-score, without false positives. By integrating structural learning with topological reasoning, this method enables accurate and automated HT detection in complex ICs.

This paper proposes a joint frequency-time domain anti-jamming circuit architecture for GNSS receivers, employing an FFT/all-phase FFT (FFT/apFFT) integrated phase difference method to detect multiple continuous wave interferences and estimate their frequencies. To address the high hardware resources and power consumption of traditional methods, this work develops an efficient FFT/apFFT integrated phase difference method with reverse-conjugated preprocessing. Algorithmic simulations demonstrate equivalent detection performance between the proposed and traditional methods. DC synthesis results in 40 nm CMOS technology reveal 25.69% area reduction and 35.73% power savings compared to baseline designs.

Thermal radiation (TR) has emerged as a promising technique for post-silicon hardware Trojan (HT) detection. However, existing TR-based methods rely on complex analyses of thermal radiation maps (TRMs), resulting in significant time overhead. To this end, we propose the TURBO framework, which performs TRMs feature fusion via the U-Net architecture for batch detection of high-volume ICs. TURBO leverages U-Net’s ability to extract and integrate multi-scale TR features, effectively distinguishing HTs from vacant regions. Experiments show that TURBO achieves over 95% detection rate for pixel-level HTs under 130 nm and 28 nm nodes, with a runtime of 4 minutes for 10⁵ pixels.