Vector processors are widely used in high-performance computing (HPC) due to their flexibility and energy efficiency. However, their performance scaling is increasingly constrained as silicon technology approaches its physical limits. This paper investigates carbon-based arithmetic units as a promising alternative for vector processors. Through simulations, we demonstrate that CNT arithmetic unit achieves 33% lower latency than silicon at the 0.5 μm node. And at sub-10 nm technology nodes, CNT-based designs exhibit a 7× speedup compared to conventional silicon FinFET implementations. These results highlight CNT’s superior scaling characteristics and its strong potential as a next-generation computing technology.

Cascaded active EMI filters offer superior suppression performance compared to single-stage filters, but the required number of components increases proportionally with the number of stages, resulting in larger volume and higher cost. To address this issue, this paper proposes a multi-channel active common-mode EMI filter based on magnetic core and chip reuse. In the proposed structure, multiple cascaded filter modules share a single current-sensing magnetic core, effectively reducing the number of magnetic components and lowering both hardware cost and structural complexity. Additionally, by employing a dual-channel high-speed operational amplifier (AD826), the design enables chip-level reuse in the signal amplification stage, further improving integration and compactness. A dual-feedback cascaded architecture is adopted to enhance common-mode EMI suppression without significantly increasing hardware resources. Experimental results based on a boost converter platform validate the effectiveness of the proposed filter in achieving both high suppression performance and efficient component utilization, making it well suited for power electronic systems operating in complex electromagnetic environments.

This paper discusses a design methodology for achieving both galvanic insulation and gate voltage transfer for high-voltage power semiconductor using resonant inductive wireless power transfer. In the proposed approach, both control and power signals are transmitted simultaneously via magnetically coupled coils. The minimum required separation distance between the coils to ensure adequate insulation is first evaluated through electromagnetic field simulations, considering the system’s high-voltage requirements. Subsequently, analyses using the proposed gate drive circuit are conducted for coils of various geometries and sizes. At a given amplitude for both the control and high-frequency power signals, the maximum allowable transfer distance is analyzed to determine the conditions under which the gate-drive voltage required for the power-side SiC MOSFET can be reliably achieved. Furthermore, the influence of coil geometry — such as winding type, turn count, and physical dimensions — on system performance is examined to identify configurations that optimize coupling efficiency and minimize losses.

To overcome the issues of large overshoot and slow response commonly associated with conventional integral sliding mode control in speed regulation, this paper proposes a novel nonlinear integral sliding mode control strategy based on an improved reaching law for the integral sliding surface. Firstly, this paper optimizes the traditional integral sliding surface and the exponential reaching law, and evaluates their stability through Lyapunov stability analysis. Subsequently, based on the optimized sliding surface and reaching law, a Nonlinear Integral Sliding Mode Controller (NISMC) is developed. Finally, an experimental platform is established to conduct verification and comparative analysis. The experimental results demonstrate that the proposed NISMC strategy significantly enhances dynamic response and disturbance rejection capability.

To achieve efficient parallel computation in the computing-in-memory array, simultaneous activation of multiple wordlines is required to load multiple input feature vectors. Consequently, the load of the charge pump applied to the WL drivers also undergoes frequent changes. This paper presents an adaptive-compensated charge pump for flash-based computing-in-memory, that significantly improves its transient response. The charge pump can be dynamically compensated in response to load variations. This design is implemented in a 55-nm CMOS process with 0.053 mm² layout area. According to the post-layout simulation, the worst steady-state ripple is 0.96 mV at 7-V output voltage and the recovery time (99.9%) is 52 ns at the load change of 25 pF.

We developed a simple and cost-effective solution for millimeter-wave waveguide component production, using additive manufacturing (3-D printing) with plastic plating technology in W-band. The 3-D printing is based on a selective laser sintering technology. In this paper, we demonstrate operation of a 105-GHz-band WR-10 BPF. The BPF is based on a fourth-order Chebyshev BPF with a bandwidth of 9.04 GHz, and an insertion loss of 0.66 dB at the center frequency of 103.3 GHz.

A 12-bit capacitor weight self-calibration successive approximation analog-to-digital converter (SAR ADC) is presented. The amplifier structure with Output-Offset Storage (OOS) technology is used to optimize circuitry to lower comparator offset voltage and noise. The bottom-plate sampling suppresses charge injection, thereby improving linearity and noise performance. The design also employs capacitive weight self-calibration with a proposed sign-aware two’s complement mapper, which enhances the ADC’s signal-to-noise-and-distortion ratio (SNDR) to 72.09 dB and demonstrates excellent conversion accuracy. The proposed ADCs were fabricated in a 0.18 μm 1P6M CMOS process. It consumes 36.8 mW, occupies an active area of 1117 μm × 717 μm using 1.8 V supply and the sampling rate of 3 MS/s.

This paper presents a Closest-Value-Substitution Digital Pre-Distortion(CVSDPD) Method for Current-Steering digital-to-analog converters(DACs). The proposed approach relies solely on offline sampling to select input code whose output values are closest to the ideal, without requiring complex digital calibration circuitry, elaborate error modeling, or prior knowledge of the DAC architecture. This makes the method both versatile and low-cost. MATLAB simulations demonstrate that the proposed method can reduce the static mismatch-induced INL to 1.5 LSB. Furthermore, silicon measurements on a 16-bit DAC fabricated in a 28nm-CMOS process show that the CVSDPD technique improves the SFDR by more than 12 dBc, achieving up to 82 dBc at low frequencies.

This letter presents a 26.9-71.9 GHz low noise amplifier (LNA) using a current-reuse technique for mm-wave applications. The proposed LNA consists of two stages. The first stage uses a feedback structure to extend bandwidth, with series inductors introduced to enhance high-frequency response. The second stage incorporates a series LC network to expand output matching bandwidth. High-pass and low-pass filters are utilized to achieve broadband input matching. Operating at 2.5 V supply voltage, the LNA consumes 15.7 mW, achieving 19.0 dB gain with over 45 GHz bandwidth. The simulated results demonstrate 2.9 dBm OP1dB, 6 dBm IIP3 (FoM = 15.67), and 4.22 dB NF @ 50 GHz. The core area of the layout is 0.29×0.16 mm².

This paper presents an innovative miniaturized filtering coupler design methodology. Targeting device miniaturization and reconfigurability, the approach creatively integrates two open-circuited stubs into microstrip coupler branches based on microstrip transmission line theory and low-pass filter prototypes. This achieves functional integration of filtering and coupling capabilities. Both simulation and measurement results demonstrate excellent performance. The proposed method is adaptable to design filtering couplers across various frequencies and dimensions.

This paper presents a 28-GHz four-way differential Doherty power amplifier (PA) implemented in 40-nm CMOS technology. A distributed active transformer (DAT)-based interstage quadrature divider (DIQD) is introduced to minimize insertion loss and enhance power gain. Additionally, a DAT-based single output transformer (DSOT) is proposed to achieve low-loss, compact power combining, and load modulation simultaneously. Measurement results demonstrate a P_sat of 22.6 dBm, an OP1dB of 21.2 dBm, a peak PAE of 20.5%, and 14.2% PAE at 6-dB PBO at 28 GHz. With a 100-MHz 64-QAM modulated OFDM signal, the PA achieves an average output power of 13.5 dBm and an average PAE of 9% at an EVM of -25 dB. With a 400-MHz 64-QAM modulated OFDM signal, it delivers an average output power of 11.3 dBm and an average PAE of 8% at -25 dB EVM.

This brief proposes two compact tunable bandpass filters (TBPFs) based on the switchable varactor-based resonators. Due to the difference in resonance equations between the two modes of the switchable resonators, the proposed filter can operate at lower frequency bands without significantly increasing its size. Varactor diodes and switching diodes are utilized at the resonator and the positions of feed lines, which remain the coupling coefficients and external quality factors almost constant throughout the entire tuning range. For demonstration, a two-pole Filter A with a frequency tuning range from 0.77 to 1.11 GHz and 1.83 to 2.24 GHz is designed and measured. 1-dB fractional bandwidth (FBW) remains at 4.5 ± 0.2%. The core circuit size is only 0.08λg × 0.17λg. Filter B, based on the optimization of Filter A, achieves continuous tuning within the 1.1 to 2.25 GHz range, with a fractional bandwidth of 4.7 ± 0.3%. The core circuit size is 0.09λg × 0.19λg.

In this letter, a novel double-gate silicon-on-insulator (SOI) Lateral Insulated Gate Bipolar Transistor with P-pillar (DGP LIGBT) is proposed and investigated by TCAD simulation. The proposed LIGBT structure employs a P-pillar and the N-type carrier stored layer under the P-well, which shows a better compromise between the forward voltage drop (V_on) in the on-state and the turn-off time in the off-state. The proposed DGP LIGBT exhibits the maximum value of the breakdown voltage by virtue of the assisted depletion effect induced by the P-pillar. Meanwhile, the results of the simulation demonstrate that turn-off time of the proposed DGP LIGBT can be decreased by nearly 24.2% and 50.0%, respectively, compared with the double-gate LIGBT (DG LIGBT) and the conventional LIGBT at the same forward voltage drop of 0.91 V. Moreover, the latch-up immunity of the proposed LIGBT structure is significantly improved owing to the optimized hole current path at the cathode.