A cross-symmetric main&tail inductor with high area utilization is proposed originally. The proposed cross-symmetric main&tail inductor improves the area utilization by using the redundant area of the octagonal main inductor while optimizing the LC-VCO phase noise. Compared with the conventional inductor, the unit area utilization rate is increased from 82.84% to 87.13%. Phase noise is achieved as -129.5 dBc/Hz over LC-VCO based on the cross-symmetric main&tail inductor, which is lower than -120.4 dBc/Hz of the conventional inductor. The output frequency range of the LC-VCO is 2.295 GHz~3.080 GHz, and FOM of LC-VCO is 193.8 dBc/Hz.

Logarithmic multipliers offer hardware efficiency but suffer from significant errors. This brief proposes a high-accuracy design using a WCE-minimizing compensation algorithm that dynamically selects the larger operand for optimal scaling. The resulting compensation value enables direct error correction without additional adders. Zero-padding exploitation facilitates bit-width truncation, reducing barrel shifter and adder complexity while preserving accuracy. Compared to prior designs, the multiplier achieves minimal normalized mean error distance (NMED) and mean relative error distance (MRED) with near-optimal power-delay product (PDP), establishing an optimal accuracy-efficiency tradeoff. Additionally, it induces a double-sided error distribution that mitigates excessive error accumulation in multiply-accumulate applications.

This paper presents a fifth-order inverse Chebyshev bandpass filter (BPF) operating at 600-840 MHz, realized using a stacked glass-based Integrated Passive Device (IPD) technology featuring Through-Glass-Vias (TGVs). The architecture employs a vertically stacked topology that enables the independent optimization of 3D TGV inductors and Metal-Insulator-Metal (MIM) capacitors, which are integrated via a high-precision chip-to-wafer bonding process. The fabricated BPF achieves an exceptionally compact footprint of 0.012λ₀ × 0.008λ₀, a sharp shape factor (SF) of 2.62, and a low insertion loss of 1.26 dB. These results represent a superior combination of miniaturization and selectivity compared to other filters realized on competing substrates. This work demonstrates a scalable methodology for co-integrating high-performance passive components on glass interposers, advancing the development of 2.5D/3D ultra-high-density heterogeneous systems by significantly enhancing integration density and RF performance.

This letter presents a novel comma detection module and an optimized parallel 8b/10b decoder for the JESD204B receiver. The presented architecture is characterized by low power and small area. Thereinto, the distributed detection methodology as well as logical decomposition method are proposed for overcoming the complex circuitry of the comma detection module and reducing its power consumption. Furthermore, the parallel 8b/10b decoder is based on the combinational logic, while the Quine-McCluskey (Q-M) algorithm is applied to simplify the decoding logic. The proposed architecture occupies 2952 μm² and 0.58 mW, decreasing by 36% and 27% respectively compared with typical architecture. The simulation and implementation results demonstrate that the proposed controller can achieve the comma detecting and decoding functions.

Ferroelectric field effect transistor (FeFET) is one of the non-volatile memories (NVMs) and offers significant advantages in Computing-in-Memory (CiM) digital circuit design. However, in existing non-volatile logic designs, the FeFET gate voltage and internal switch state are usually used as equivalent logic inputs. The different input variable forms limit the cascading and computational efficiency of the operation. To address this problem, this brief proposes a FeFET-based unit circuit, which performs built-in less-than comparison according to the gate-source voltage of FeFET. The proposed unit circuit can be combined with CMOS logic gates to implement a non-volatile comparator and can be extended to both serial and parallel fully non-volatile comparators. The simulation results indicate that compared with other non-volatile comparators, the FeFET-based comparator is more suitable for IoT applications in terms of computational efficiency and data recovery capability in power-off environments.

This paper presents an enhanced parameter-adaptive Q-learning algorithm with triple phase-shift (TPS) modulation for dual-active-bridge (DAB) converters, where limitations of traditional algorithms in achieving global optimum are overcome. TPS control provides three degrees of freedom through internal phase-shift angles, enhancing flexibility to reduce current stress and conduction losses under light-load conditions. However, power-loss-model-based TPS modulation requires complex computations under complicated conditions involving varying loads and voltage conversion ratios. This work proposes an enhanced parameter-adaptive Q-learning based modulation strategy which efficiently obtains the global optimal solutions. By leveraging frequency-domain unified phasor analysis, the optimization process avoids the manual mode selection associated with voltage conversion ratios and load conditions. The algorithm implements adaptive parameter updates within a phased framework by phase-based reward functions and sequence-adaptive ε-greedy strategy. Finally, experimental results demonstrate efficiency improvements of 3% and 8% under rated-load and light-load respectively.