A new zero space orthogonal projection (ZSOP) method is presented to synthesize the antenna array pattern. The expected pattern vector is divided into two parts, the main lobe vector and the side lobe vector. In order to maximize the side lobe attenuation, the optimal solution of the antenna element excitation vector should be placed in the zero space of the side lobe steering matrix. Therefore, the optimal solution of the antenna element excitation vector must be in the orthogonal projection space of the conjugate transpose matrix of the side lobe steering matrix. Thus, the pattern synthesis equation can be transformed into a new form. The solution of the new equation can ensure that the optimal solution of the antenna element excitation vector can form a pattern with an extremely low null beam level. Examples are used to demonstrate the advantages of the new method. Simulation results show that the new method can form patterns with excellent null beam levels that far exceed the performance of other methods. The new method can work with non-iterative calculation steps. It requires only slightly more computation amount than the traditional least square method to complete the pattern synthesis task.

Capacitive-type level transducers are widely employed due to the increasing demand for level monitoring in various industrial systems. Accurate modeling of these transducers is crucial for improving their measurement performance. This paper introduces an equivalent circuit model for capacitive-type level transducers that accounts for the internal edge effect, addressing limitations of traditional models, which often overlook the actual conditions between the inner and outer electrode bases. Furthermore, this paper proposes a novel analytical approach based on electromagnetic field analysis to characterize the internal edge effect. To validate the proposed model, a capacitive-type level transducer was fabricated, and performance was tested using several prototypes with varying distances between the inner and outer electrode bases, leveraging finite element method (FEM) simulations and experimental results.

Due to its simplicity in circuit implementation, conventional Data Weighted Averaging (DWA) is commonly used to calibrate capacitor mismatch in feedback DACs. However, for low-amplitude input signal, the non-random use of capacitor elements causes periodic mismatch errors, leading to harmonic distortion in the signal band. Consequently, this results in significant harmonic distortion within the signal band. This paper proposes a randomized DWA algorithm that utilizes the amplitude of the input signal to control the starting position of DAC elements for each cycle, thereby suppressing tones caused by DAC element mismatches. Compared to the conventional DWA algorithm, this approach achieves higher linearity while reducing DAC switching activities. To evaluate the proposed algorithm, a second-order discrete-time sigma-delta modulator model was designed. Simulation results indicate that the proposed algorithm achieves up to a 14% reduction in switching activities and extending the dynamic range by approximately 5 dB compared to the conventional randomized DWA algorithm.

Physical Unclonable Functions (PUFs) represent a promising hardware security technology, particularly under resource-constrained conditions. However, conventional Arbiter PUFs (APUFs) are highly vulnerable to machine learning (ML) attacks. To address this limitation, this paper proposes an innovative PUF circuit design scheme leveraging parallel delay arbitration. The approach involves constructing a two-tiered APUF architecture, where the delay differences of individual path segments are extracted for arbitration. The final PUF response is obtained by XORing the arbitration results, thereby enhancing the linear complexity between the circuit’s challenges and responses. This significantly improves the PUF’s resistance to ML-based attacks. Experimental results demonstrate that even with a training set comprising 10⁶ challenge-response pairs and employing various ML models for attacks, the prediction accuracy remains substantially lower than that of a 3XOR-PUF with comparable hardware resource utilization. Moreover, the proposed PUF circuit exhibits excellent performance across other critical metrics, achieving a stability of 98.03%, while maintaining nearly 50% randomness and uniqueness.

This paper presents a design method aimed at enhancing the high-efficiency fallback range of ultra-high-power Doherty power amplifiers. This method integrates 27 mm and 36 mm gate-width chips into a dual channel device by optimizing the internal matching design. It employs an asymmetric design combining a power input ratio of 1:2 and a power ratio of 2:3 to extend the fallback range and minimize efficiency degradation. Additionally, an enhanced Π-type double impedance matching and fifth-stage post-matching design were proposed to address the limitations of narrowband performance. Finally, a 470 W asymmetric Doherty power amplifier based on GaN HEMT was developed. The measured results indicate that within the 2.50-2.75 GHz frequency range, the amplifier achieves a saturated output power of 56.3-56.7 dBm, a linear region gain of 17.2-17.9 dB, and a saturated drain efficiency of 68%-73%. At an 8 dB power back-off, the drain efficiency ranges from 59% to 64%. This method presents an effective scheme for achieving a high-efficiency fallback range in ultra-high-power Doherty amplifiers.