Swimming is one of the most popular worldwide sports, which offers the players healthy body, improved fitness, and endless enjoyment due to its easy accessibility and year-round availability. Monitoring swimmers can aid in the development and participation of swimming sport. However, due to the difficulty of in-water monitoring, the existing methods in tool box are still limited. In this paper, a more accessible wearable monitoring system based on a flexible piezoelectric device is developed. This system collects muscle contracting and relaxing information by measuring its generated force on a Polyvinylidene fluoride (PVDF) sensor. Then the information is transmitted via a low-frequency radio frequency (RF) signal to the receiver on land. This information is analyzed using a convolutional neural network and the classification of different strokes is realized. The system also supports monitoring at two positions by wearing multiple devices on the body. By integrating data from multiple positions, the analysis algorithm achieves a higher prediction accuracy of over 95%. This work demonstrates that the combination of wearable monitoring devices, the Internet of Things, and Artificial Intelligence, which holds significant promise for sports education, research, promotion, and development.

This study develops new technology for detecting metal foreign objects to enhance the safety of wireless charging systems. The intrusion of metal objects during charging may result in reduced performance, increased energy consumption, and excessive heat generation, which may potentially damage the charging system. In this paper, we develop an innovative sensorless method of detecting foreign objects. We build an efficiency model by conducting experiments with metal objects of various sizes placed between charging coils. This approach identifies metal objects on the basis of efficiency changes, eliminating the need for sensors, thus effectively reducing costs. Finally, the effectiveness and reliability of this model are validated using the experimental platform.

This paper proposes a voltage-controllable switched reluctance generator (SRG) system with a ring winding structure driven by a full-bridge power converter, which is the first application of a full-bridge power converter to drive the SRG. The proposed topology inherits the advantage of low copper loss of the ring winding that combines AC and DC currents together. It connects the equivalent DC power provided by a DC-DC half-bridge circuit to the ring winding to provide circulating DC and partial excitation energy. This paper provides a detailed description of the proposed system’s feedback loops and operating principle. The proposed topology is compared with the uncontrollable Circulating-Current-Excited Switched Reluctance Generator (CCEG). The comparative study is validated through simulation and experimental platform, and the results highlight the output voltage performance of the proposed topology and control method.

In order to improve the flexibility of the current protection circuit operation, a current protection circuit that can change the current limit value by adjusting the resistance value of the external resistor is designed. The load current is sampled using a sense-FET sensing circuit designed with an improved common-source common-gate current mirror, which reduces losses while ensuring the accuracy of the current limit value. The current is processed through two different branches to improve the efficiency of fault handling. The design is implemented using a 0.18 μm BCD process. Simulation results show that at a supply voltage of 12 V, current limit range of 1 A~5 A, the accuracy is less than 0.96% affected by temperature, the fast shutdown time is about 70 ns, and the completion of the protection time is about 1 μs.

This paper presents an all-MOS ring oscillator with a temperature compensation circuit, which can be integrated into a microcontroller unit (MCU) chip. We suppose a compensation circuit to mitigate the frequency drift caused by temperature fluctuations. The absence of resistors and capacitors in the oscillator can significantly reduce the layout area. In addition, the current-starved circuit minimizes power consumption and enabls flexible frequency adjustment. The design has been simulated using a 180 nm CMOS process, resulting in a layout area of the oscillator less than 0.00495 mm². Experimental results also demonstrate that the oscillator achieves a stable clock of 350 MHz at a voltage-controlled input of 850 mV. Furthermore, across the temperature range of -40°C to 125°C, the maximum frequency variation remains between -0.88% to +0.297%. The oscillator’s power consumption is as low as 0.315 mW.

In this paper, a contact pressure online monitoring method of PP-IGBT based on the ultrasonic measurement is proposed. A finite element (FE) model of PP-IGBT is established. The dynamic contact pressure within PP-IGBT during power cycling process is analyzed based on the FE model. An ultrasonic measuring system for contact pressure measurement of PP-IGBT considering the structure of the device and fixture is designed. A temperature compensation method using coupling interface reflection wave is proposed to eliminate the influence of temperature on measuring the contact pressure. A power cycling test platform is established to verify the effectiveness of the proposed method. Results show that the proposed method can realize the non-invasive online measurement of the contact pressure in PP-IGBT.

A high-efficiency power amplifier (PA) and a high-conversion-gain (G_c) upconverting mixer (UCM) were developed using 75-nm InP-based MOS HEMTs to enable sub-THz beamforming with a sufficiently large equivalent isotropic radiated power (EIRP) and effectively suppressed grating lobes. The chip sizes of both millimeter-wave monolithic integrated circuits (MMICs) were minimized to less than 1 mm, facilitating their integration into a sub-THz phased-array (STPA) transmitter with an antenna pitch of one wavelength or less, specifically less than 1 mm at 300 GHz. The PA MMIC demonstrated superior performance compared with conventional PAs in the 300-GHz band owing to advanced manufacturing technologies, including the use of a modulated passivation film alongside the gate oxide and epitaxial structures. A peak power-added efficiency (PAE) of 9.3% was achieved, with an associated output power of 9.2 dBm and a linear gain of 18.6 dB at 300 GHz. To the best of our knowledge, the achieved PAE is the highest reported to date. Moreover, the UCM MMIC, which comprised a third-order subharmonic resistive mixer, an on-chip band-pass filter, and an RF amplifier, operated with a 5-dBm local (LO) signal at 90 GHz. The MMIC demonstrated a high G_c of -1.9 dB, a 3-dB bandwidth spanning 39 GHz (270-309 GHz), and a 1-dB gain-compressed RF power of -10.4 dBm, with a power consumption of 84 mW. The observed 3LO leakage power was -26.5 dBm. These findings indicate that a higher EIRP can be achieved with reduced power consumption through the use of an STPA transmitter that integrates a Si CMOS IC and an InP-based MMIC based on the circuits described here.

Many electronic devices such as smartphones can now utilize wireless charging. Most of the power transmitting and receiving coils built into these devices are single-layer planar spiral coils to make them lighter and thinner. However, manufacturers have difficulty determining whether or not to wind the coil all the way to the center and what the inner diameter of the coil should be. In this paper, we clarify the various electrical and physical properties given by different inner diameters and present the optimal inner diameter ratio for power transfer efficiency. The analysis results show that the optimal inner diameter ratio for obtaining the maximum power transfer efficiency in the resonant frequency range of 100 to 200 kHz is 0.288 to 0.391 when the outer diameter is 43 mm.

This paper presents a 2.4 GHz receiver front-end employing a 3× passive subharmonic mixer and a polyphase filter (PPF) to achieve low power consumption. We proposed a new subharmonic mixing technique in this study to design the mixer. Given that the generation of multiphase local oscillators (LO) is challenging in passive subharmonic mixing, we proposed a new PPF that can generate the LOs at lower cost compared to previous works. Consequently, a standard LC oscillator can work in conjunction with this receiver front-end. This work is designed with 65 nm CMOS technology and the post-simulation shows the power consumption of this receiver is 340 μW, noise figure is 6.27 dB and IIP₃ is -27.3 dBm.

This paper presents a circuit implementation of a dual-dither strategy that combines calibration dither and linearization dither to effectively address the correlation between calibration performance and input signal amplitude, while mitigating amplifier output compression and range redundancy caused by multi-level dither injection. Specifically, we propose the ‘Roving Star’ scheme, which generates a multi-bit, uniformly distributed, and uncorrelated dither signal. Additionally, we propose a threshold voltage dithering circuit with a wide-range adaptive adjustment reference voltage to correct residual curve deviation resulting from the mismatch between flash and multiplying digital-to-analog converter (MDAC) reference voltages. These advancements were successfully implemented in a 500 MS/s 14-bit pipelined ADC fabricated with a 40 nm CMOS process. The implementation resulted in significant performance improvements, notably increasing the SFDR from 69.4 dB to 89.2 dB and enhancing the SNDR from 65.6 dB to 70 dB.

A push-pull buffer with source degeneration output structure is proposed as an intermediate stage for an output capacitorless low-dropout regulator (OCL-LDO) in this paper. The proposed push-pull buffer with source degeneration output structure can increase the current for charging and discharging the gate capacitance of the power transistor during the transient instant, effectively improving the transient voltage slew rate at the gate of the power transistor, thereby enhancing the transient response of LDO. Additionally, a transient overshoot reduction (TOR) circuit is employed to suppress the overshoot phenomenon during transient response. The proposed LDO is implemented using 0.18 μm CMOS technology. Simulation results indicate that the LDO can operate from a supply voltage of 1.2-1.8 V with a minimum dropout voltage of 0.2 V at a maximum 50 mA load and quiescent current of 22 μA. With a load current step from 200 μA to 50 mA within 10 ns, the maximum value of the voltage spike is 160 mV and the maximum recovery time of the LDO is 0.88 μs.

With advances in CMOS technology, the threshold voltage variation has worsened, which has a bad impact on the timing variation for sense amplifier enable signal. This paper proposes an oscillator replica bitline (ORB) technique for suppressing timing variation of SRAM sense amplifiers. The number of MOSFETs used in the ORB technology is approximately 40% of that in conventional replica bitline technique and the ORB technique can be programmed to modify sense amplifier enable timing. The simulation results show that, at a supply voltage of 0.8 V, the timing variation can be reduced by approximately 52.37% and 6.29% compared with the conventional replica bitline technique and replica bitline with multistage technique, respectively.

This paper presents an output capacitor-less LDO regulator (OCL-LDO) with high PSR and ultra-low quiescent current. The circuit utilizes a local feedback amplifier based BGR and a pseudo-dynamic biased error amplifier to improve its PSR. Hereinto, the modified super source follower solves the stability problem in the local loop and further reduces the output impedance. Furthermore, the nested miller compensation based on dynamic nulling resistor (DNR-NMC) is utilized to keep stable in the full load range. The transient enhancement circuit can reduce the overshoot and outshoot voltage by 68% and 35%, respectively. This design implemented in 180 nm technology occupies an area of 0.132 μm² and provides a controllable output over a supply range of 2.5 V-5 V and the maximum output current is 100 mA. The PSR is less than -75 dB at 100 Hz and -40 dB at 10 kHz with the load current of 100 mA. Additionally, the line regulation and load regulation are 0.08%/V and 0.21%/A, respectively.

In this study, we developed a high-frequency electric field imaging system based on the first-order electro-optic effect for the detection of time-varying frequency wave sources. The proposed system utilizes the optical heterodyne technique. The process begins with an antenna that detects the frequency of the electric field of interest, which is then fed into the optical local oscillator (LO) signal generation system. This optical LO signal tracks the frequency of the electric field being observed while maintaining a constant intermediate frequency. This configuration enables the visualization of dynamic electric fields, including asynchronous wave sources and frequency-modulated signals, without requiring a direct physical connection to the wave source.

In this paper, a novel on-chip digital soft-start circuit is proposed to realize the suppression of inrush current and overshoot voltage in the startup phase of the system based on the idea of intermittent charging of an on-chip capacitor. The circuit was simulated and implemented using the 0.18 μm BCD process. Simulation and test findings reveal that the soft-start time is 2 ms, the layout area occupied by the circuit is 0.018 mm², the soft-start circuit can suppress peak inrush current by up to 87.3%, reducing the inrush current to below 634 mA, and there is no overshoot in the output voltage. The proposed architecture does not consume system power and is fully integrated on the same chip without any external components, which effectively reduces the die size and the cost.

In this paper, a four-channel 14bit 10M/S TI SAR ADC with 1.8 V power supply voltage and 1 V reference voltage is implemented on the Cadence platform. At the same time, a calibration method based on fully connected neural network is proposed. After the error analysis of the designed ADC, the random mismatch is introduced to the capacitance array (CDAC) and the PVT combination simulation is carried out in the center frequency range of ±1% to obtain multiple sets of error data as network training data and test data. The back propagation (BP) algorithm is used to train the neural network until the network converges, 11 sets of data are input for testing. The test results show that the average effective number of bits (ENOB) and spurious-free dynamic range (SFDR) are improved by 4.72 bits and 34.17 dBc respectively after calibration, and the network also has a calibration effect on input signals other than training frequency.