How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3 s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

Ping-Pong auto-zero (AZ) amplifiers require high-speed switching to amplify with high frequency signals. In Ping-Pong auto-zero amplifiers, a Common-Mode Feedback (CMFB) technique, in which the two-input Common Sense Amplifiers (CMSA) of the Common Sense (CMS) blocks are shared by using a sample-and-hold circuit, is often used. This configuration is effective for reducing transient switching of the output common-mode voltages. However, this technology requires a multi-phase clock, which complicates the clock generation circuit and makes it difficult to increase the switching frequency. This letter describes the phase number reduction technique in Ping-Pong AZ. The proposed technique reduces the required phase number to two phases by using a 4-input CMSA instead of a 2-input CMSA. Furthermore, the impact on offset due to the change to the 2-phase configuration can be mitigated by inserting an integrator into the AZ loop, thereby limiting the increase in σ to 1/6.06.

This letter presents a 2548-μm² CMOS temperature sensor. It uses a self-regulated capacitively-biased dynamic threshold MOS (DTMOST) and a simple CTAT reference source as front-end to generate a temperature-dependent clock signal, which is then fed into a counter-based frequency-to-digital converter (FDC), yielding a digital readout. Implemented in a standard 55 nm CMOS process, the sensor has 942.5 μm² front-end area, achieves an inaccuracy of ±0.89°C (3σ) from -40°C to 125°C after one-point calibration in batch. It consumes 6.15 μW and achieves a resolution of 14.5 mK and a resolution figure of merit (FoM) of 2.1 pJ・K².

This paper presents a 13-bit, 200-MS/s, two-stage pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) with separated kT/C noise cancellation and a hybrid dynamic amplifier (DA). The proposed architecture employs a coarse SAR to decouple the kT/C noise cancellation from the first-stage conversion, thereby significantly reducing both the excessive power consumption and the additional noise introduced by amplifier operation during this process. With a DA reused for kT/C noise cancellation and the first-stage residue amplification, dynamic noise suppression can be effectively achieved. In order to meet the inter-stage gain and linearity requirements, an open-loop inverter-based DA with tunable harmonic distortion cancellation is utilized as the second-stage residue amplifier. Designed in a 55-nm CMOS process, the proposed ADC achieves a 73.8 dB SNDR with 0.021 mm² core area, and has a power consumption of 1.9 mW at 200 MS/s. This yields a Schreier figure of merit (FoM) of 181 dB and a Walden FoM of 2.37 fJ/conversion-step.

This letter presents a unified phase- and voltage-domain modeling framework for type-II double-sampling phase-locked loops (DSPLLs). An improved analytical phase-domain model is derived by refining the phase detector’s transfer function. A Verilog-A based voltage-domain model is developed, enabling fast transient-only phase noise analysis. We clarify the noise contribution of the S/H clocks. We further extend the reference phase noise 3 dB-reduction theory, revealing its degradation under asymmetric sampling slew rates. The phase- and voltage-domain models validate each other and offer useful guide for DSPLLs design optimization.

This paper proposes an LED driver circuit that requires only partial power conversion. This driver consists of a buck converter. The LED current is regulated by controlling the duty cycle of the power switch. While over 70% of the power required by the LED string is directly provided by the DC power source, the buck converter only needs to convert 30% of the power to maintain a constant LED current. The input and output of the proposed buck converter are both low voltage with minimizing the voltage stress on all components. This allows the circuit to adopt the lower voltage and current rating of components, which then reduces cost and size. Since both input and output voltages are within 5V, the components such as the power switch, diode, and resistor can be integrated into an integrated circuit, further reducing overall circuit size and cost. This article provides the circuit operating principle and analysis. A simulation circuit is also designed for an LED lamp consisting of three LEDs. The simulation results verify the feasibility of the proposed LED driver circuit.

A single-ended to differential low noise amplifier (LNA) for Beidou satellite communication applications based on standard 40 nm RFCMOS technology is reported. On-chip L-C parallel tank load and source degenerated inductor are used in the first-stage single-ended amplifier to reduce the influence of TX leakage signal on the input of LNA. The pseudo-differential cascode amplifier with an inductor as tail current source and 4-terminal symmetric mode octangle inductor as load are adopted in the second-stage to output differential signals and achieve sufficient gain. The two-stage differential series-parallel L-C notch filters are respectively added to the differential common-source output and the common-gate output to suppress the strong TX interference signal. The simulation results show that the LNA achieves S21 18.2 dB, NF 2.2 dB, and S11 -11.5 dB at 2.491 GHz. The interference signal rejection ratio is 44.8 dB at 1.6 GHz. The static power consumption is only 6.16 mW with a size of 1.931×1.332 mm² including testing pads.

This paper presents a high slew-rate operational transconductance amplifier (OTA). The slew-rate enhancement (SRE) circuit is separated into two paths for dynamic current boosting. The main path provides dynamic bias current, while the other auxiliary path applies dynamic current to the output of the core amplifier. Therefore, both the slew rate and the settling response can be improved. By utilizing the hybrid dynamic current boosting technique in a current-mirror amplifier, simulation results show that the average SR is increased by more than 10 times, and the average 1% settling time is reduced by more than 50% with less than 38.6% power consumption overhead. The proposed OTA and two other OTAs using different SRE techniques have been fabricated in a 0.18-μm CMOS process. Measurement results have proved that the proposed design has the best overall performance.

Battery management system as core components of mobile power supplies and energy storage systems, rely critically on the precision of their analog-to-digital converters (ADCs) to optimize battery performance. This paper addresses resistor mismatch issues in resistor DACs for battery management chip ADC, arising from process variations, proposing an adaptive calibration method. The approach dynamically compares voltages of resistors under calibration with reference resistor-divided voltages, utilizing successive approximation logic to control series/parallel trimming resistors and mitigate mismatch induced accuracy degradation. Based on the 0.35 μm commercial BCD process, a 12-bit, 20 kPS SAR ADC for a battery management chip has been designed and comprehensively verified. The verification results shows that, under actual process variations, the adaptive calibration method reduces the DNL range from -2.7 +3.3 LSB to -0.3 +0.4 LSB, and the INL range from -2.2 +2.7 LSB to -0.3 +0.4 LSB. ENOB achieves 11.22 bits, SINAD reaches 69.33 dB, SFDR is 74.98 dB.

Substrate integrated waveguide (SIW) provides an attractive solution to the integration of planar and nonplanar circuits by using a planar circuit fabrication process. However, it is difficult to achieve a small size and broadband on the basis of a single-layer SIW. Herein, we propose a compact substrate integrated waveguide filter with E-shaped slot line resonators (ESRs) etched on the top of SIW cavities, which achieves broadband and miniaturized bandpass. Moreover, out-of-band rejection has been improved. The SIW filter with a chip size of 7.6 mm × 3.6 mm × 0.4 mm has the center frequency of 24 GHz and respective passband width of 3 GHz fabricated by micro-electro-mechanical systems (MEMS) technology. Measured results of this filter exhibit a high selectivity and a maximum in-band insertion loss of approximately 1.8 dB.

The adiabatic Physical Unclonable Function (PUF) utilizes adiabatic logic principles and CMOS process variations to achieve low energy dissipation and improved security for Internet of Things (IoT) applications. In this work, a low-power 6-transistor (6T) adiabatic PUF circuit is designed, and its performance is evaluated through simulation and chip measurements using a Rohm 0.18 μm CMOS technology. Simulation results indicate that the circuit achieves an average reliability of 98.93% under temperature variations, along with a uniqueness of 49.75% and an energy dissipation of 15.92 fJ per challenge cycle per bit when the bodies of the PMOS transistors are connected to V_dd. Furthermore, by eliminating one transistor and one phase of the power clock compared with the conventional low-power two-phase adiabatic design, the proposed circuit achieves a smaller implementation area while maintaining low-power dissipation. To verify the functionality of the design, a 4-bit chip was fabricated and tested. The measurement results demonstrate correct operation, with an average reliability of 96.92% at room temperature and a uniqueness of 51.67% with the body connected to V_dd.

In this letter, we propose a method to design wideband high-efficiency power amplifiers (PAs) based on extended continuous Class-B/J (ECCB/J) modes with a new low-pass filter (LPF). This LPF consists of many E-shaped resonators. Its capability to control harmonic impedance matching allows for improvements in both efficiency and bandwidth. And it can also contribute to a broadband impedance matching in the predefined optimal impedance region with the combination of ECCB/J modes. To verify the proposed methodology, we designed and fabricated a wideband high-efficiency PA using a commercial 10-W GaN device. The measured results show that in the target frequency band from 0.5 to 3.0 GHz, a drain efficiency (DE) of 58.5%-78.5% and a gain of 9.6-12.2 dB can be obtained and a saturated output power of 39.6-42.2 dBm when the input power is 30 dBm.