W-band (75–110 GHz) metasurface-integrated phased arrays suffer from non-scalable beam-control design due to prohibitive optimization cost. This letter proposes a deep-learning-assisted optimization framework for beam control in W-band metasurface-integrated phased arrays. A physics-informed convolutional neural network (CNN) surrogate is developed to learn the nonlinear mapping from unit-cell geometry to transmission response, enabling efficient gradient-based inverse design and rapid metasurface phase synthesis. Using the proposed framework, a 20×20 metasurface-assisted phased array operating at 94 GHz is designed and numerically validated. The surrogate model, trained on 18,600 full-wave simulated unit-cell samples, predicts transmission phase and amplitude with mean absolute errors of 3.47 and 0.021, respectively, while reducing the inverse-design time to 1.8 ms per cell, corresponding to a 96.4% reduction in computational cost. The optimized array achieves continuous beam steering from −38.5° to +41.2° with realized gain variation within ±1.2 dB, up to 4.8 dB sidelobe reduction, and improved radiation efficiency across the steering range. These results validate deep-learning-assisted metasurface optimization for high-performance beam control.

This letter proposes a deep–narrow time delay neural network (TDNN) architecture for efficient microwave transistor modeling. The proposed approach incorporates a generalized activation function with four learnable parameters, enabling flexible adaption of the activation function into various forms, including standard sigmoid, adaptive sigmoid, swish, adaptive swish, and other variants tailored to meet specific modeling requirements. Such flexibility can further improve the modeling accuracy of the deep TDNN model. In addition, to efficiently train the deep TDNN model utilizing typical transistor measurement data, analytical formulations for direct current, small-signal S-parameter, and large-signal harmonic outputs of the proposed TDNN are derived. A three-stage training algorithm is also proposed to effectively train the deep TDNN model. The effectiveness of the proposed method is validated through modeling examples of microwave transistors and the application in power amplifier analysis.

This study investigates the Single-Event-Burnout characteristics of p-GaN HEMTs through combined heavy-ion irradiation experiments and numerical simulations. Experimental results reveal distinct responses: the 100 V-rated device exhibited a progressive rise in leakage current, indicating severe degradation yet successfully avoiding catastrophic burnout up to a fluence of 1×10⁷ ions/cm². In contrast, the 200 V-rated device exhibited SEB failure at a drain bias of approximately 100 V, which corresponds to half of its rated voltage. To elucidate the underlying physics, TCAD simulations were performed. The analysis suggests that the failure is driven by a positive feedback loop involving radiation-induced hole accumulation. Specifically, holes generated by high-LET particles accumulate at the buffer interface, causing severe electric field distortion that triggers avalanche multiplication and subsequent thermal destruction. These findings highlight the critical role of electric field management and offer guidance for optimizing radiation-hardening strategies in next-generation GaN power devices.

This article presents a foreground calibration technique to mitigate the interstage gain error induced by the non-ideal voltage division (NVD) effect in noise-shaping (NS) pipeline successive-approximation-register analog-to-digital converters (SAR ADCs). The proposed method employs a hybrid-domain feedback loop that adjusts the reference voltage via 9-bit coarse digital-to-analog converters (DAC), effectively suppressing the leakage of first-stage quantization noise without requiring invasive modifications to the core analog path. To ensure long-term stability against charge leakage at high-impedance nodes, a periodic refresh strategy is implemented with negligible power overhead. Furthermore, a comparator reuse technique is adopted to eliminate offset errors. Validated in 40-nm complementary metal-oxide-semiconductor (CMOS) technology, the calibration improves the signal-to-quantization-noise ratio (SQNR) from 76.57 dB to 90.30 dB and achieves a spurious-free dynamic range (SFDR) of 95.77 dBc. The robustness of the proposed technique is verified by Monte Carlo analysis, demonstrating a post-calibration gain accuracy of 0.2% (3σ).

Voltage-mode constant-on-time (V-COT) buck converters are widely adopted for powering high-performance XPUs due to their superior transient performance. Small-signal modeling is essential for evaluating their stability and dynamic behavior. While the conventional describing-function (DF) method is commonly used, it involves a cumbersome derivation and fails to provide an explicit expression for the loop gain. Luckily, emerging sampled-data modeling features a simpler derivation. However, existing work focuses on V-COT without external slope compensation, a feature indispensable in practical applications to suppress subharmonic oscillations. To address this gap, this paper establishes a comprehensive small-signal model for V-COT control with external slope compensation using the sampled-data modeling method. Based on the proposed model, an explicit expression for the crossover frequency is derived, providing a direct theoretical foundation for bandwidth design and ramp-slope optimization. Simulation and experimental results validate the accuracy of the developed models.

To address cryptographic chips’ requirements for high parallelism, robust stability, and flexible operation, this paper proposes a novel multi-port reconfigurable shift register file (RSRF). It adopts an enhanced 14-transistor (14T) memory cell and differential read circuit to boost noise immunity, with optimized transistor sizing to enhance speed while preserving stability. An integrated configurable shift network allows flexible switching between storage mode and multiple shift operations. Post-layout simulation in 40 nm CMOS at 1.1 V and 25°C demonstrates a maximum frequency of 2.3 GHz, power consumption of 4.69 mW, and a core area of 0.021 mm². Compared to prior designs, the proposed architecture delivers high performance and multi-port access while enhancing noise margin and process robustness. By integrating in-memory computing, this work offers a new approach toward efficient cryptographic hardware.

In this study, an ultrawideband rectifier for wireless power transmission (WPT) is proposed. The basic circuit with two capacitors and two diodes was analyzed as an initial candidate for the ultrawideband rectifier. In this case, a large value for the capacitance of the direct current (DC) cut capacitor was effective in achieving a wide bandwidth characteristic. Subsequently, the microstrip lines after the diode were adjusted, and an inductor was added to further broaden the bandwidth. The rectifier was fabricated as a double-voltage circuit using microstrip lines. The RF–DC conversion efficiency of 54% was recorded when the DC load resistance was 200 ohm and the input power was 20 dBm. The frequency response measurements showed a frequency bandwidth of 0.012 to 5.700 GHz and a fractional bandwidth of 199.2% (RF-DC conversion efficiency ≧ 50%) when the DC load resistance was 500 ohm and the input power was 18 dBm, resulting in the ultrawideband characteristics.

This letter proposes a multifunctional distributed Brain-Machine Interface (BMI) system. The system achieves bidirectional communication and power delivery over a single shared coaxial network. To realize multi-functionality, four stimulation and recording functions were integrated into a CMOS core chip fabricated in a 180 nm standard process. A 23.5 x 7.5 mm prototype unit device was fabricated for functional verification. Results demonstrated 40 µA-resolution stimulation and an input-referred noise of 125 µV_RMS. Furthermore, simultaneous operation of two unit devices was verified, confirming the architecture’s scalability. This work provides a versatile platform for multi-point neural interfacing with minimal wiring.

This paper proposes a high-resolution analog front-end (AFE) integrating a low-noise transimpedance amplifier (TIA), a variable-gain amplifier (VGA), and a second-order 1-bit delta-sigma analog-to-digital converter (Δ-Σ ADC) followed by a three-stage digital decimation filter, realizing a resolution of 24-bit. Implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) process, the proposed AFE achieves 14.9-bit effective number of bits (ENOB) within 10 kHz bandwidth, 160 dB common-mode rejection ratio (CMRR), and 0.62 pA current resolution. Benefiting from the superior isolation of the FD-SOI process, the proposed design offers efficient multi-channel scalability while preserving exceptional noise performance and dynamic range.

This paper presents a sensorless Adaptive On-Time (AOT) controlled buck converter that achieves fast transient response without inductor current sensing. The converter operates at approximately 1 MHz with reduced switching-frequency variation over a 3.0–3.6 V input range, a 1.5–2.5 V output range, and load currents from 100 mA to 500 mA. The proposed converter is implemented in a UMC 0.18-μm 1P6M CMOS process with a chip area of 798.66 × 614.3 μm². Simulation results show undershoot and overshoot voltages of 23 mV and 36 mV, with recovery times of 1.66 μs and 2.94 μs, respectively. The switching-frequency variation is limited to within ±3%, and the peak efficiency reaches 97.71%.

This paper presents the reduction characteristics of penetration electromagnetic fields of a square slot aperture owing to parallel wires when a plane wave is incident on the square aperture. An integral equation for the aperture magnetic current was derived and solved using Galerkin’s method of moments. Three cases of wire loading were discussed as single, double, and triple loadings on the square slot. The results show that the asymmetric triple loading case is a good structure for reducing the transmission because of its wide frequency range with minimum penetration fields. Experimental results are presented to validate this theory.

We present a comprehensive study on ultra-wideband impedance matching using exponential tapering of transmission line characteristic impedance. The analysis models the tapered region as cascaded sections represented by ABCD matrices and evaluates the reflection performance across a broad frequency range. A shaping factor is introduced to optimize the taper profile, minimizing the required physical length to maintain VSWR < 1.1. The study spans multiple load-to-source impedance ratios from 1.5 to 10, determining the optimal shaping factor for minimum exponentially tapered profile, which consistently outperforms linear profiles in impedance matching and compactness. Our study offers clear, ready-to-use taper parameters for microwave designers.

This paper presents a clock and data recovery (CDR) circuit based on a single-loop, half-rate architecture that operates without a reference frequency. Both the reference clock and a separate frequency detector (FD) are eliminated by integrating a frequency direction detection function and mode-switching control into the phase detector (PD). This approach enables a wide frequency capture range with bidirectional frequency tracking and fast acquisition. The proposed CDR is designed and simulated in 28-nm CMOS technology, occupying a core area of 0.061 mm² and consuming 20.2 mW from a 1-V power supply. Simulation results demonstrate a wide locking range from 6 to 14.2 Gb/s, a fast acquisition rate of 22.78 (Gb/s)/μs, and a peak-to-peak jitter of 7.6 ps for the recovered clock at 14.2 Gb/s.

Near-infrared (NIR) spot tracking has emerged as a critical technology for precision applications. However, the realization of sub-micron detection with high responsivity is limited by low NIR photon energy. To overcome this, we propose a practical approach that incorporates localized surface plasmon resonance (LSPR) effects into silicon-based position-sensitive detectors (PSDs). By optimizing Au nanoparticle dimensions (50–60 nm) under an external field, efficient hot-carrier collection is realized. The proposed device demonstrates a remarkable responsivity of 2.42 A/W at 1010 nm, a high positional accuracy of 19.05 μm, and exceptional position resolution of 0.5 μm.

This work presents a three-stage wideband cryogenic low-noise amplifier (LNA) with a noise matching extension technique, fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) process. To achieve wideband noise matching, a current-reuse inverter topology is adopted to reduce the noise parameter Rn at cryogenic temperature (CT). Additionally, dual source-degeneration is employed for wideband input matching. The LNA was packaged and characterized at both room temperature (RT) and CT. Measurement results demonstrate that, at 16 K and over the 0.5–5 GHz band, the LNA achieves an average noise temperature of 14.8 K, a peak gain of 39 dB, and a total power consumption of 5.6 mW. The total chip area is 0.7 mm², including all pads.

This paper presents a low power, low phase noise ring digitally controlled oscillator (DCO) for 2.4 GHz Internet-of-Things (IoT) all-digital phase-locked loops (ADPLLs). The core comprises two stages of differential delay cells and a digital-to-analog converter (DAC). The delay cell employs a noise cancellation technique to reduce the phase noise of the DCO. Coarse tuning is achieved using a 3-bit MIM switched capacitor array, while fine tuning is realized via an 8-bit R-2R DAC that generates the tuning voltage V_tune to control an IMOS varactor pair, enabling monotonic capacitance tuning. Implemented in TSMC 65 nm CMOS technology, the DCO exhibits an output frequency tuning range of 2.38–3.07 GHz. At 2.38 GHz, the phase noise is −92.53 dBc/Hz at a 1 MHz offset with a power consumption of 3.46 mW. A frequency resolution of 85 kHz is obtained, and stable phase noise characteristics are maintained across process, voltage, and temperature (PVT) variations. The chip occupies an area of 0.037 mm².

In this paper, a lumped-element dual-band bandpass filter (D-BPF) is designed and fabricated based on Liquid Crystal Polymer (LCP) technology. The proposed D-BPF allows for independent tuning of transmission zeros via adjustable inductors and capacitors, enabling flexible passband control. It is fabricated on a 4-layer LCP substrate with dimensions of 7.5 mm×5.1 mm×0.193 mm. The measurement results show that the center frequencies and insertion losses of the two passbands are 2.94 GHz/1.2 dB and 5.24 GHz/2.29 dB, respectively, which meet the requirements of mobile communication and WLAN. The compact size and low insertion loss indicate that the proposed D-BPF is suitable for application in the RF front-end system.