Modern General-Purpose Graphics Processing Units (GPGPUs) leverage massive Thread-Level Parallelism (TLP) to hide memory and computation latencies. However, static scheduling policies, such as Round-Robin (RR) or Greedy-Then-Oldest (GTO), struggle to adapt to the dynamic pressure on execution units, leading to unbalanced resource utilization. Existing schedulers typically overlook the congestion status of backend units (e.g., ALU and Load/Store Unit) and fail to exploit the instruction type information available at the frontend. This oversight can cause schedulers to issue instructions to already congested units, inducing pipeline stalls while leaving other units idle. To address this, we propose RPAWS (Resource-Pressure Aware Warp Scheduler). RPAWS employs an I-Buffer lookahead mechanism to identify the next instruction type (Compute vs. Memory) for each warp, dynamically classifying warps into a compute queue or a memory queue. Simultaneously, it monitors the real-time busyness of backend units and dynamically adjusts the priority of these queues: prioritizing the compute queue when the memory unit is congested, and vice versa. Experimental results demonstrate that RPAWS improves performance by an average of 22.7% and reduces pipeline stalls by 19.7% compared to the baseline. Furthermore, RPAWS requires only minimal additional storage and logic.

To address voltage overshoot, uncontrolled resonant current, and ZVS failure during startup of high-ratio DC LLC converters caused by parasitic capacitance and effective Q-factor surge, this paper proposes a three-stage soft-start strategy: pre-charge for gentle voltage buildup, open-loop ramping with precise duty cycle calculation to ensure ZVS, and closed-loop steady-state output locking. An equivalent model incorporating transformer parasitic capacitance is established to analyze the mechanism of virtual voltage overshoot, with key parameter design formulas derived. A prototype with a 12 V input and a 180 V output validates the strategy’s effectiveness in suppressing startup impacts, achieving full-process ZVS and smooth voltage buildup. This offers an engineering solution for the reliable startup of high-gain LLC converters.

This paper proposes a compact filtering crossover based on a circular substrate-integrated waveguide (SIW) cavity with integrated orthogonal cross transitions and an air cavity. By removing the central copper cladding and incorporating a cross transmission structure, the design achieves a passband with improved signal transmission and frequency selectivity within a single cavity. Two orthogonal feeding ports are introduced to exploit degenerate modes, providing simultaneous filtering and crossover functionality with high isolation. The device operates from 8.0 GHz to 9.1 GHz, corresponding to a fractional bandwidth of 12.9%, with a return loss better than 25 dB and an insertion loss below 2.0 dB. Furthermore, replacing the dielectric with an air cavity enhances thermal management and reduces footprint, making it suitable for RF front-end applications. Experimental results demonstrate the design’s effectiveness, showing improved isolation and lower insertion loss compared to conventional multi-cavity architectures.

Achieving a low temperature coefficient (TC) remains challenging in voltage reference design. This paper proposes a piecewise curvature correction based on temperature points adjustment to address this issue. The method adjusts the calibration temperature points and performs piecewise compensation on the first-order reference, tuning the output voltage at each point to reduce TC. The proposed circuit is implemented in 0.18 µm BCD technology. Under SS, TT, and FF corners, the temperature drift is reduced to 27.7%, 53.2%, and 76.1% of its original value, respectively, validating the effectiveness of the proposed piecewise curvature correction technique. To enhance the power supply rejection ratio (PSRR), a self-biasing reference supply is adopted in this work, resulting in a PSRR of −98.1 dB at 100 Hz.

IoT ultraviolet (UV) sensors face an intrinsic tradeoff between ultralow power sensing and energy demanding signal amplification. To resolve this, we report a back illuminated n doped GaN photodetector operating at a near equilibrium 0.1 mV bias voltage, achieving an ultralow 6 pW static power. Utilizing trap assisted photogating effect, the device yields a high 6.42 A/W responsivity and robust nanoampere scale currents. Furthermore, structural photonic engineering enables 365 nm narrowband spectral selectivity with a 21.75 nm full width at half maximum (FWHM). This unamplified configuration directly interfaces with low power analog to digital converters (ADCs), dramatically reducing system level energy overhead for fully sustainable IoT UV monitoring.

We demonstrate a fabricated stateless RISC-V optical intermittent platform integrating photovoltaic harvesting, supercapacitor buffering, PMU-gated power management, and a UART-programmable RISC-V core. By replacing fixed-function sensing/control logic with a small software-programmable CPU, the platform supports more flexible on-node processing under harvested intermittent power without requiring checkpointing or state-retention hardware. After each interruption, the system restarts from a known boot state. Because the platform is powered directly by an optical harvesting source rather than a programmable supply, it enables realistic charge-operate-shutdown characterization. Waveform-level measurements confirm repeatable operation over more than 300 consecutive intermittent cold-start cycles, with no bit errors observed in an ID-transmission workload, indicating deterministic restart under harvested energy. Measured intermittent behavior includes 50–697 s charge times as a function of light level, a regulator rise time of approximately 20 μs, and an average operating window of 1.17 s across 37 cycles.

This paper presents a non-isolated high-gain DC–DC converter utilizing a parallel-charged cumulative-discharge boost configuration with a 1:1 coupled inductor for photovoltaic (PV) panel integration with a 48 V DC-bus. The proposed operating principle enables parallel inductor energization and series energy transfer enables a high voltage gain at a reduced duty ratio. For a 48 V output, the converter operates at 29.2% duty ratio while limiting switch voltage stress to 36 V. A quasi-distributed air-gap magnetic design is adopted to mitigate fringing-related proximity losses. A 200 W, 50 Hz prototype achieves 95.8% peak efficiency and stable MPPT under varying irradiance and partial shading conditions.

The deployment of large language models (LLMs) on edge devices is constrained by computational and memory overhead. While rotation-based low-precision quantization addresses some limitations, matrix-multiplication-based rotation operations with O(N²) complexity introduces new performance bottlenecks. Replacing these operations with the Fast Walsh–Hadamard Transform (FWHT) reduces computational complexity to O(Nlog₂(N)), but this method remains inefficient on scalar processors. To address this, we propose FWHT-RVV, a RISC-V vector processor with FWHT instruction extension for edge LLM inference. The proposed approach employs a blockwise hybrid FWHT algorithm to minimize data permutation and reduce memory access overhead. Furthermore, we introduce specialized vector instructions to reduce data movement costs. Experimental results demonstrate a 2.55x average speedup and a 2.52x improvement in energy efficiency compared to the baseline vectorized implementation, with only a 0.80% increase in hardware area.

This paper presents a novel dielectric waveguide connector for millimeter-wave bands, covering frequencies from 26.5 GHz to 40 GHz (WR-28 band). A connector for direct connection between two dielectric waveguides was designed and measured. Experimental results show that an insertion loss in the WR-28 band is below 0.5 dB, demonstrating good characteristics and is in good agreement with simulation results.

For program memory in SoC designs, a critical challenge lies in minimizing retention leakage power and simultaneously optimizing both read operation and write robustness. In contrast, write speed and write power can be traded off. Based on these characteristics, this brief presents a fast read and robust write SRAM for program memory with ultra-low retention leakage. This SRAM employs a novel single-ended 10T bitcell featuring fast read, robust write, and ultra-low retention leakage, complemented by a control-signal maintenance circuit to ensure stability during post-retention power-up. To further verify the proposed design, the 10T SRAM was fabricated in a 22 nm FDSOI process. Measurement results demonstrate that the SRAM can operate at a supply voltage as low as 0.33 V, with a corresponding read energy of 17.14 fJ/access-bit and a read frequency of 1.4 MHz at this voltage. Meanwhile, this SRAM retains data down to 0.24 V, with a retention power consumption of 0.029 pW/bit under this condition.

This letter presents a broadband GaN Doherty power amplifier (DPA) operating in continuous Class-J mode using a phase-controlled impedance synthesis methodology. The proposed method simultaneously constrains both fundamental and second harmonic impedances, explicitly incorporates the carrier amplifier’s intrinsic parasitic impedance, and performs a global co-design of the phase compensation line, output matching network, and post-matching network. The DPA achieves 60–80% drain efficiency at saturation and 45–58% at 6 dB back-off across 1.6–2.9 GHz (58% fractional bandwidth), with 12–13 dB gain and 43–44.5 dBm saturated output power. The moderate back-off efficiency variation reflects the inherent wideband design trade-off. Under a stringent 100-MHz 5G NR signal without digital predistortion, the ACPR ranges from −37.5 to −22.5 dBc at 36 dBm average power.

Increased operating temperatures significantly compromise the reliability of high-density printed circuit boards (PCBs). While traditional thermal evaluation methods struggle with efficiency under complex conditions, machine learning offers a robust alternative through nonlinear modeling. This paper develops a weighted fusion model (WFM-LBS) for predicting the thermal performance of high-power-density PCBs. By integrating Linear Regression with Gradient Descent (LR-GD), Back Propagation Neural Network (BPNN), and Support Vector Regression (SVR) as base learners, the model utilizes the Entropy Weight Method (EWM) to optimize weight assignment. Comparative validation demonstrates that WFM-LBS effectively synergetizes the strengths of individual predictors, significantly enhancing prediction accuracy and stability. This approach provides a reliable foundation for real-time thermal monitoring and intelligent management of high-performance cooling systems.

The frequency-modulated continuous wave (FMCW) light detection and ranging (LiDAR) is a powerful tool for measuring long distance and velocity. However, its in-plane spatial resolution or frame rate is inherently limited by the round-trip time of light. We propose a parallel operation of FMCW LiDAR using the wavelength division multiplexing and Pound–Drever–Hall (PDH) technique without sacrificing optical power and clarity of control. As proof of concept, two laser diodes are wavelength multiplexed, and their lasing frequencies are simultaneously modulated by PDH error signals generated using a scanning Fabry–Perot interferometer. The two parallel three-dimensional measurements successfully generated a doubled spatial resolution of FMCW LiDAR.

This paper presents a 2 × 32 Gb/s 128-Gb/s/mm single-ended distributed transimpedance amplifier fabricated in a 28-nm CMOS processing technology. To address the area-bandwidth trade-off inherent in conventional distributed amplifiers, a distributed biasing scheme is proposed to eliminate large passive terminations and their associated layout overhead. In addition, a dual m-derived inductor-peaking technique is introduced to extend the bandwidth without channel width penalty. The prototype achieves a per-channel data rate of 32-Gb/s, a 3-dB bandwidth of 24 GHz, a transimpedance gain of 42.9 dBΩ, and an edge bandwidth density of 128 Gb/s/mm.