This paper proposes a quasi-constant on-time control method with adaptively tuned on-time. It offers three key advantages: 1, regardless of the equivalent series resistance magnitude of the output capacitor, it achieves inherent system stability without requiring ramp compensation, significantly simplifying the design; 2, it maintains a constant quality factor, thereby enhancing both system stability and transient response performance, particularly under wide-input-output-range conditions; 3, the switching frequency variation is limited to a maximum of twofold, thereby mitigating the impact of electromagnetic interference noise. SIMPLIS simulation results validate the correctness and feasibility of the proposed method.

Inspired by the biological brain, neuromorphic hardware has gained significant attention due to its higher energy efficiency. Network-on-Chip (NoC) architecture offers an excellent and scalable solution to implement large-scale spiking neural network hardware. Efficient routers are essential to ensure the high energy efficiency of NoC-based neuromorphic hardware. In this paper, a low power dual routing table multicast-supported router is proposed for large-scale NoC-based neuromorphic hardware. Experimental results demonstrate that the proposed multicast scheme reduces transmission time by more than 62.2% compared to unicast. The router achieves an ultra-low energy consumption of 4.4 × 10⁻² pJ/bit and a compact area of 0.011 mm².

Dual-directional silicon-controlled rectifiers (DDSCRs) are attractive for bidirectional ESD protection due to their high robustness, compact size and down-scaling potential. However, aggressive scaling of the central N-region to improve area efficiency inevitably leads to critical punch-through leakage current and simply expanding the spacing will result in a reduction of area efficiency. To resolve this trade-off, a novel DDSCR utilizing a compensation doping technique is proposed and verified in a 180 nm BCD process. The suppression mechanism is validated via TCAD simulations. TLP measurements demonstrate that the proposed DDSCR reduces leakage current by over five orders of magnitude (from over 1 mA to 10 nA) without any silicon area penalty, while preserving high robustness and bidirectional protection capability. This work provides an effective solution for suppressing punch-through leakage in ESD protection applications.

In this paper, we propose a novel bipolar voltage and current pulse generation converter (BVCP-GC) for the resistance welding applications by combining a phase-shifted full-bridge converter and a new multi-function pulse generator. The proposed BVCP-GCT consists of a phase shifted full bridge (PSFB) converter as the first stage and the proposed multi-functional pulse generator as the second stage, which can generate unipolar and bipolar voltage pulses as well as unipolar and bipolar current pulses. The detailed operation principles and key characteristics of the proposed converter are also given. Finally, a reduced experimental prototype was developed. Experimental results verify that the proposed converter can generate positive-voltage pulses, negative-voltage pulses, bipolar-voltage pulses, and bipolar-current pulses.

This paper introduces a level shifter designed for high-voltage DC–DC buck converters. Compared with the conventional level shifter, the proposed level shifter incorporates a novel digital control scheme that actively selects the output signal that first meets the logic threshold, whether rising or falling, thereby significantly enhancing both propagation delay and delay matching. Furthermore, enhanced noise immunity is achieved by the clamping isolation MOSFETs during high dV/dt transitions. Implemented in a 0.18 μm BCD process, post-layout simulation results indicate a propagation delay of 0.58 ns, a worst-case delay mismatch of 0.07 ns, and a dV/dt immunity of 350 V/ns.

Accurately predicting the magnetostriction of nanocrystalline alloy laminations is crucial for analyzing high-frequency transformer core vibration and noise. To resolve the magnetic circuit asymmetry in existing single-yoke measurements, a high-frequency magnetostriction testing system for nanocrystalline laminations is designed with a double-yoke configuration, adopting a mirror-reflected L-shaped laser path to achieve precise measurement under high-frequency sinusoidal excitation. To overcome the limitations of traditional simulation models relying on single physical mechanisms or pure data-driven approaches, a universal dynamic magnetostriction simulation method based on the Energetic-PSO-LSTM coupled model is proposed. Comparative verification shows that at 0.5 T, the coupled model’s RMSE is reduced to 0.69, significantly improving prediction accuracy and validating its reliability.

The conventional deadbeat predictive control systems for permanent magnet synchronous motors (PMSMs) often suffer from speed fluctuations. To address this issue, a novel composite control strategy is proposed. Firstly, a composite regulator is introduced for the speed loop. This regulator consists of a frequency-adaptive regulator module and a proportional gain module connected in parallel. Secondly, deadbeat predictive control method is employed to enhance the dynamic performance of the PMSM system. Finally, an experimental platform was built to conduct comparative tests between the composite control method and the conventional deadbeat predictive control method. Experimental results demonstrate that the composite control strategy significantly reduces the speed fluctuations.

The growth in 5G mm-Wave communications draws tremendous demands on the high-quality signal sources. To satisfy the requirements for a wide tuning range and low phase noise, PLL cascaded with a frequency multiplier is typically applied in mm-Wave systems. In this letter, a 9–13 GHz integer-N charge-pump PLL (CPPLL) is designed, which could cooperate with a frequency tripler and a 6-GHz intermediate frequency to fully cover the 5G mm-wave FR2 frequency bands. In the PLL design, a parallel inductor is used in the voltage-controlled oscillator (VCO) to avoid its Q-factor degradation, thus improving the phase noise performance. Additionally, thick-oxide transistors are employed to extend the CP output voltage range, which could increase the PLL tuning range with a relatively small varactor, and in turn improve the VCO tank Q-factor. Besides, the small varactor could reduce the VCO gain, which can suppress the reference spur. The proposed CPPLL is fabricated in a 65-nm CMOS process with a core area of 2.6 mm². With measurements, the PLL demonstrates a 36.36% frequency tuning range from 9 to 13 GHz, and achieves a jitter of 80.9 fs and a reference spur level of −72.27 dBc. With a typical power consumption of 31.2 mW, the CPPLL achieves −246.9 and −241.8 dB figure of merit (FoM) and figure of merit with tuning range (FoM_T), respectively.

This paper presents the design and characterization of two 16-bit (4×4) single-poly EEPROM arrays based on different 4T memory cell architectures fabricated in a 0.18-μm BCD process for power management IC applications. Both memory cells employ Fowler–Nordheim tunneling for program and erase operations and are fully compatible with the baseline BCD process without additional masks. The 4T-Inv array provides rail-to-rail voltage readout with low static current and supports simultaneous readout of all 16 cells, while the 4T-Sel array offers current-mode sensing with a compact array implementation. Experimental results demonstrate stable array-level operation, endurance over 1000 program/erase cycles, and acceptable retention at 150°C.

Mamba2, as one of the most promising variants of state space models (SSMs), has shown remarkable performance in various domains. However, accelerating Mamba2 on existing hardware architectures is still challenging due to its inefficiency in processing element-wise (EW) operations. In this work, we propose PMSCA, which uses parallel computing arrays to accelerate sparse Mamba2 models. Firstly, we use a dynamic bit-width scaling strategy and weight pruning method to significantly reduce memory overhead. Additionally, sparse computing based on weight pruning greatly improves the throughput of matrix multiplication. Secondly, we propose a hybrid layer-wise N:M structured pruning method to reduce the accuracy loss of weight pruning. Thirdly, we propose a unified multi-branch structured state space duality (SSD)-post-processing element (PPE) architecture to improve the computing efficiency of element-wise operations, thus achieving parallel computation of element-wise operations and matrix multiplications within SSD. What’s more, we propose a well-designed mapping and parallel hardware scheduling strategy to balance workload and further improve efficiency. Compared with the Intel i7-14700k CPU and Nvidia RTX-4090 GPU, our design achieves 68–192×/3–74× speedup of SSD, 23–53×/0.7–12× speedup of Mamba2, and 1655–3618×/44–816× higher energy efficiency, respectively.

An ultra-low-power and temperature-insensitive power-on reset (POR) circuit based on a reference current and a current comparator is proposed in this paper. The circuit employs a subthreshold MOS-based reference current generator and a current comparator to achieve accurate reset signal generation. Implemented in a standard 180-nm CMOS process, the circuit consumes less than 1 nW of static power. A voltage detector composed of stacked diode-connected transistors and series MOS capacitors enhances both transient and steady-state responses, reducing sensitivity to supply ramp rates. The proposed circuit features a programmable delay scheme to improve stability. Experimental results demonstrate a stable trip voltage of 1.24 V, a static power consumption of only 0.443 nW, and a temperature coefficient of 186.7 μV/°C over the temperature range of −30°C to 125°C. Compared with recent POR designs, this work achieves the lowest static power consumption.

To prevent potential damage to ADC input circuitry from excessive RF front-end output signal strength in modern receivers, this letter presents an ultra-low OP1dB wideband buffer LNA for signal level control at the ADC interface. Designed with an adjustable low-gate-voltage bias, negative feedback, and current-reuse techniques, the LNA was fabricated in a 0.15-μm GaAs pHEMT process. An average gain of 19.5 dB is measured across 1–6 GHz, with average OP1dB of −0.4 dBm and average OIP3 of 11 dBm. The chip occupies 1.5×1.0 mm².

In this letter, a novel resistive-reactive extended series of continuous inverse modes (Res.-Rea. ESCIMs) theory is proposed to address the drain efficiency (DE) and output power degradation problems in the conventional broadband power amplifier (PA) design. Two adjustable factors λ and μ are introduced into the existing dual current magnitude regulation factor as a compensation solution. They can enhance DE and output power, and further expand the impedance design space (IDS). This new theory can guide the design of high-efficiency broadband PAs. A multi-octave continuous inverse mode PA is fabricated and measured. The measured results show that a DE of 60.5%–75.5% and an output power of 39.2 dBm–43 dBm are achieved within 0.8 GHz–3.7 GHz. The measured adjacent channel power ratio (ACPR) is lower than −24 dBc at 1.1, 1.4, 1.7, 2.0, 2.3, 2.6, 2.9, 3.2, and 3.5 GHz when the output power is lower than 38 dBm.