Audio noise suppression techniques are commonly utilized across diverse audio systems, often relying on general-purpose processors. However, this leads to inefficiencies in terms of hardware resource usage, energy consumption, and overall system expense. This paper presents a specialized microcontroller for audio noise suppression, based on the Hummingbird E203 framework. Key hardware optimizations include enhanced multiplication and division units using Booth4 encoding, Wallace tree, and dual SRT-4 mechanisms, alongside the integration of an F instruction set for floating-point operations. A camouflage strategy reduces memory transaction complexity. Software improvements utilize adaptive spectral subtraction for efficient noise suppression. Benchmarks show a 4002.5% boost in floating-point performance and significant gains in noise reduction, with a 54.6% decrease in noise energy and a 28.7% rise in signal-to-noise ratio, highlighting its efficacy.

This paper proposed back propagation neural network (BPNN)-based design of digital analysis filters to cancel the aliasing errors caused by the non-ideal characteristics of analog mixers and filters in hybrid filter bank digital-to-analog converter (HFB DAC). Initially, we establish a mathematical model for HFB DAC to derive the ideal and actual transfer functions, which is used to calculate the estimation error between the ideal and actual transfer functions. Then, the approximation error is obtained by summing the real and imaginary parts of the estimation error. Finally, the BPNN is used to minimize the approximation error, thereby obtaining the optimal coefficients for digital analysis filters to achieve the aliasing errors cancellation. In addition, this paper derives the computational complexity of BPNN. The simulation results show that our proposed BPNN-based design of digital analysis filters achieves better aliasing errors cancellation than the weighted least squares (WLS)-based, WLS+Optimization-based and minimax using second order cone programming (SOCP) designs at the cost of increased computational complexity.

Logic locking is a technique designed to safeguard integrated circuit netlists from security threats. However, recent advancements in machine learning-based structural attacks have significantly challenged existing logic locking methods. Moreover, current defenses against these structural attacks often diminish the resilience of logic locking against Boolean satisfiability-based attacks (SAT attacks). To address this limitation, this paper presents the Depth-Coupling Logic Locking (DCLL) technique. DCLL utilizes a key to control a multiplexer and an XOR gate, establishing a robust interconnection at the functional level. By incorporating subgraph replacement, DCLL enhances both the locking mechanism and its resistance to SAT attacks. Experimental results reveal that DCLL achieves an exponential increase in SAT attack resistance while maintaining robustness against machine learning-based removal attacks. Furthermore, DCLL provides a balanced defense against oracle-guided (OG) and oracle-less (OL) attacks. For circuits with one million gates, DCLL incurs minimal overheads of 0.37% in area and 0.40% in power, positioning it as an efficient and effective solution for enhancing the security of logic locking techniques.

Adder neural networks (AdderNets), a promising lightweight alternative to traditional CNNs, face the “memory wall” challenge in von-Neumann architectures. Computing-in-memory (CIM) has emerged as a promising solution to address this memory bottleneck. This work proposes a novel spin-transfer torque magnetic random-access memory based digital-CIM macro tailored for AdderNets mapping, leveraging Boolean logic-optimized architecture to seamlessly integrate storage and computation. The architecture is validated through simulations under 40 nm CMOS technology. Results show that the architecture achieves an energy efficiency of 39.48 TOPS/W in 8-bit network inference, representing a 1.4× to 2.0× improvement over state-of-the-art digital CIM designs.

This paper proposes a fault detection algorithm addressing both common open-circuit faults and unique continuous current faults in three-phase full-bridge switches for SRM with ring winding structure. By employing a decoupling computation of three-phase winding currents, fault signatures independent of operational state variations are derived. Following fault detection, adaptive thresholds dynamically adjusted with motor operating conditions are implemented for current analysis, enabling precise identification of fault types and locations through advanced signal processing. The developed methodology achieves online automatic diagnosis of conventional open-circuit failures and SRM-specific continuous faults in the power conversion system. Experimental validation under varying speed and load conditions demonstrates the algorithm’s rapid response, diagnostic accuracy, and robust performance consistency, confirming its effectiveness for real-time fault monitoring in SRM drive applications.

Binary matrix-vector multiplication (BMVM) is a key operation in post-quantum cryptography schemes like the Classic McEliece cryptosystem. Conventional computing architectures incur significant energy efficiency loss due to data movement of large matrices when handling such tasks. Resistive memory (RRAM) non-volatile compute-in-memory (nvCIM) is an ideal technology for high energy-efficient BMVM processing but faces challenges, including signal margin degradation in high input-parallelism arrays due to device non-idealities and high hardware overhead from current readout and XOR operations. This work presents a RRAM nvCIM architecture featuring: 1) 1T1R cells with high-resistive-state compensation modules; and 2) pulsed current-sensing parity checkers. Based on the 180 nm process and test results from RRAM devices, the computing accuracy and efficiency of the architecture are verified by simulation. The proposed architecture performs high-precision current accumulation with a maximum MAC value of 10 and achieves an energy efficiency of 1.51TOPS/W, offering approximately 1.62× improvement compared to an advanced 28 nm FPGA platform.

This brief presents a high-performance 1-GHz frequency generator that combines a custom-fabricated 500-MHz high-fundamental-frequency (HFF) quartz resonator with a low-noise frequency doubler circuit. The HFF resonator, developed using an optimized MEMS process, achieves a high quality factor and excellent thermal stability. The monolithically integrated circuit, fabricated in 0.18-μm CMOS, successfully generates the target 1-GHz output while preserving signal integrity. Experimental results validate the design, demonstrating a low phase noise of -106.31 dBc/Hz at a 1-kHz offset and an RMS jitter of only 82.7 fs (integrated from 12 kHz to 20 MHz). The generator also exhibits outstanding stability, with frequency deviations of less than ±1 ppm for a 10% supply voltage change and within ±60 ppm over the -55°C to +125°C temperature range. These results confirm the effectiveness of combining HFF resonators with custom IC design to create high-performance timing solutions for demanding applications.

This paper proposes a compensation method based on the changes of driving current in each pixel unit, by detecting the current of organic light emitting diode (OLED) with a pulse counting and calculating the difference between the counted pulse number and target pulse number under the corresponding gray level, then generating the compensated data and converting to source output voltage to drive OLED emitting. Meanwhile, the compensated data is written into a lookup table which can be reused. This method can perform initial brightness calibration on each pixel unit by the panel maker and can also be used to compensate for the emitting current degradation of pixel units after manufacturing. Since proposed method directly compensates for the current of each pixel, it can reduce the brightness attenuation and unevenness of active-matrix organic light emitting diode (AMOLED) panel caused by various nonideal factors, thereby improving the display quality and extending the product life.

Increasing the switching frequency can reduce the size of energy storage components such as the PFC inductor and capacitor, thereby improving power density. However, this also increases switching losses and leads to severe thermal stress. To address this issue, a rectifier-type CRM-PFC circuit based on GaN devices is proposed. The control scheme combines voltage-loop feedback with current-loop feedforward and eliminates the need for zero-current detection (ZCD), enabling stable CRM operation at ultra high frequencies. Based on the proposed control method, Zero-Voltage Switching (ZVS) is achieved across a wide input voltage range. Experimental results show that the proposed PFC circuit achieves a maximum output power of 3.6 kW. The switching frequency spans from 287 kHz to 500 kHz, with a peak efficiency of 97.1% and a power factor exceeding 0.99 under full-load conditions.

Single event burnout (SEB) causes catastrophic failure to SiC power devices for power applications in space. The electrical behavior of the 4H-SiC Schottky Barrier Diode (SBD) exposed to heavy ion radiation is investigated using the Sentaurus Technical Computer Aided Design (TCAD) simulations. A “step current” is observed when the reverse current increases under heavy ion irradiation and the simulation results show the dependence of SEB on applied bias voltage, linear energy transfer (LET), and incidence angles of the heavy ion. In addition, the femto-second pulsed laser SEE facility (FPLSEE) are carried out to study the SEB characteristic of SiC SBD. The experiment results were similar to those obtained from the simulation. The electron density distribution, impact ionization distribution, and recombination distribution for SiC SBD are used to understand the possible single event burnout (SEB) mechanism involved. Results show that the SEB process in SiC SBD has both avalanche amplification respectively triggered by impact ionization and carriers recombination, and the “step” trend emerges when the two achieve dynamic equilibrium.

Lattice-based cryptography provides the security foundation for both post-quantum cryptography (PQC) and homomorphic encryption (HE). Number theoretic transforms (NTT) contribute significantly to the latency and energy consumption in cryptographic computations. This work presents a Compute-in-Memory (CIM) reconfigurable NTT accelerator for PQC and HE. The accelerator incorporates a reconfigurable array to minimize data latency, CIM processing elements to reduce memory and power consumption, and a parallel circuit for lattice-based cryptographic protocol deployment. A 28 nm chip of the accelerator consumes only 10 nJ per 256-point NTT, while achieving a throughput of 151.2 KOPS during Kyber-512 that achieves a remarkable reduction of up to 75% in clock cycles and a 70% reduction in energy consumption than the state-of-the-art.

A low-power, low-temperature-coefficient (TC), and compact bandgap reference (BGR) circuit is presented. Comparing with conventional multi-BJT structures, the proposed design employs a differential-pair voltage generator to produce proportional-to-absolute-temperature (PTAT) voltage without a large active area consumption. By compensating the nonlinear component of V_BE (base-emitter voltage), the TC is effectively reduced. The proposed BGR circuit has been implemented using a 0.18 μm technology, occupying an area of 0.027 mm². Simulation results demonstrate that at 1.2 V output, the BGR achieves an average TC of 2.83 ppm/°C over the temperature range from -40°C to 125°C, with a power consumption of merely 0.33 μW.