This paper presents a background current suppression strategy based on a redundant segmented digital-to-analog converter (RS DAC). The utilised DAC employs thermometer coding for the lower segment and binary coding for the higher segment, incorporating redundancy at the segment interface to enhance robustness against mismatch. To benchmark our approach, we conducted a Monte Carlo analysis. The results demonstrate that our suppression scheme achieves an order-of-magnitude improvement in mismatch tolerance. Additionally, A dedicated calibration algorithm was developed specifically for the RS DAC. To validate the proposed strategy, a capacitor trans-impedance amplifier (CTIA) chip was designed based TSMC 180 nm process. The measurement results confirm that the background current suppression strategy effectively reduces background current, offering a practical solution for detectors experiencing high background levels.

This letter presents a design strategy for a three-coupled transformer based g_m-boosting structure, which optimizes low noise amplifier (LNA) performance with rapid iteration design of the three-coupled transformer. The proposed strategy is used in a wideband LNA for phased array receivers operating at X-band. The three-coupled transformer based g_m-boosting structure is employed for gain and noise figure (NF) improvement, wideband input matching and a single-ended-to-differential conversion. Two CS stages are cascaded to provide higher gain and the inter-stage matching is implemented by two staggered transformers which extend the bandwidth (BW). The LNA achieves a measured gain of 21.5 dB and the -3-dB BW covers 7 to 14 GHz. The return loss is better than 10 dB across the BW. The measured NF is 3.0 dB at 7.5 GHz and the input third-order intercept points (IIP3) is -4.6 dBm at 14 GHz. The LNA occupies a core area of 0.21 mm² implemented in 40-nm CMOS process.

With the increasing demand for energy-efficient chips, various low-power flip-flops have been developed. Among these, TCFF has attracted significant attention for its ability to achieve low power consumption while maintaining overall performance. However, under advanced process technologies, TCFF faces challenges such as increased delay and potential functional failures caused by device aging. This paper proposes an anti-aging strategy for TCFF to address these challenges, leveraging the synergistic optimization of structural modification and Transistor size adjustment. Results demonstrate that TCFF exhibits reduced delay degradation across all corners. In particular, under the FF corner, the delay degradation of the rising and falling edges is mitigated by 19% and 12%, respectively. Moreover, the power-delay product (PDP) of TCFF increases by only 3.7%, while its static power consumption shows a slight reduction.

This paper proposes a BJT-based frequency-domain temperature sensor of a voltage-to-frequency converter (VFC) and error compensation. The key design is that the two base-emitter voltages from the detection front end are converted by VFC into corresponding frequency signals. To achieve high accuracy, an error compensation method calibrates errors arising from the VFC loop delay and comparator offset. Implemented in a 0.18 μm SMIC process, the sensor achieves an error of -0.35°C~+0.75°C throughout a temperature range of the -40°C~125°C. The sensor has an average conversion time of 3.5 ms, a power consumption of 270 μW, and an area of just 0.065 mm².

To reduce transmission loss in printed wiring boards (PWBs), materials with low dielectric loss tangent, such as oligo(2,6-dimethyl-1,4-phenylene ether)-based resins, are commonly used. In this study, we fabricated PWBs blending poly(2,6-dimethyl-1,4-phenylene sulfide)-based resins (PMPS-V), in which benzene rings are connected via sulfide rather than ether bonds, and evaluated its effects. The PWBs exhibited a low loss tangent of 0.0017 and achieved UL94 V-0 flame retardancy with only one-third the conventional flame retardant content. Transmission loss and eye diagram degradation up to 30 GHz were effectively suppressed after heat testing at 150°C. It was clarified that PMPS-V contributes to improving the thermal reliability of PWBs.

A 12-bit pipelined successive approximation register (SAR) analog-to-digital converter (ADC) is proposed, which operates at a sampling rate of 800-MS/s. With the assist of cross-coupled inverter pair, a gain-enhanced high-linearity open-loop residual amplifier (RA) based on gm-ratio achieves a high power efficiency and speed with complete steady-state and dynamic performance characteristics. The process, supply voltage, and temperature (PVT)-sensitive gain of RA is compensated by the adjustable bias current in the cross-coupled inverter pair. The prototype single channel ADC is integrated in an 8-channel time-interleaved ADC and implemented in a 28-nm CMOS process, which consumes 5.52 mW at 1-V supply voltage and 800-MS/s sampling rate. The measured inter-stage gain variation remains below 2% across a temperature range of -20-80 °C, achieving an SNDR and SFDR of 60.1 dB and 72.4 dB, respectively. The Walden figure of merit (FoM) is 8.35 fJ/conversion-step, and the Schreier FoM is 168.7 dB.

This work presents a 32 Gb/s tunable equalizer implemented in 65 nm CMOS. The design combines an active inductor CTLE with NCC and a source-follower buffer, overcoming the gain-bandwidth trade-off of traditional CTLEs while maintaining stable behavior under PVT variations with a DC gain variation of 5.6 dB. A 2-tap full-rate DFE further suppresses residual ISI. The results show that the proposed equalizer compensates for a 29 dB channel loss at the 16 GHz Nyquist frequency. It achieves an eye opening of 204 mV vertically and 0.77 UI horizontally at 32 Gb/s NRZ. The post-layout area is only 0.0015 mm². Furthermore, with a power consumption of only 4.6 mW, the equalizer achieves an exceptional energy efficiency of 0.14 pJ/bit.

This paper analyzes the generation mechanism of input harmonics and the inherent contradiction between bandwidth expansion and efficiency degradation in extended continuous mode. It theoretically demonstrates the necessity of implementing input harmonic control and proposes a joint input-output harmonic control technique to compensate for the efficiency sacrificed in extended continuous mode to increase bandwidth, thereby better balancing the efficiency and bandwidth performance of the power amplifier. A 1.6-2.8 GHz high-efficiency broadband extended hybrid continuous power amplifier is designed to verify this theory, with a saturation efficiency of more than 66% and a saturation power of more than 39.8 dBm.

This paper presents a Synchronized Switch Harvesting on Capacitor and Inductor (SSHCI) circuit designed for piezoelectric energy harvesting, which combines the SSHI method with the SSHC operation. Initially, the proposed SSHCI circuit employs synchronized switches to perform the SSHC operation, allowing for energy harvesting from the Piezoelectric Transducer (PZT). Following this, it transitions into the SSHI operation to invert the charges on the PZT, thereby enhancing the working voltage. Additionally, the traditional diode rectifier bridge found in conventional circuits is removed by the voltage doubling rectifier circuit to decrease the power loss. An experimental platform has been developed to evaluate the power generation performance of the proposed circuit. The results indicate that the SSHCI circuit achieves a peak power output that is 9.8% greater than that of the existing parallel SSHI circuit and 13.2% greater than that of the serial SSHI circuit, respectively.

This paper presents a high gain DC-DC converter based on multiple coupled switching inductors. The converter adopts a structure with three switching inductor units connected in series with a switching capacitor unit. Due to the conduction characteristics of the diodes, the primary sides of the three coupled inductors alternately operate in parallel and series states with the switching actions of the transistor. Furthermore, the proposed converter utilizes only a single switch, which simplifies the control strategy of the converter. Finally, in order to verify the conclusions obtained from the theoretical analysis, a prototype with an input voltage of 25 V, an output voltage of 362 V, and a rated power of 120 W is constructed.

This paper presents a novel ergodic sequential logic (ESL) neuron model capable of mimicking typical excitabilities of biological neurons and realizing excitability suitable for artificial neural networks. Utilizing this model, a novel ESL spiking neural network is presented and its learning mechanism is also designed based on the actor-critic reinforcement learning framework. It is demonstrated that the presented network can enable an agent to solve a navigation task by providing appropriate actions. Additionally, comparisons indicate that the presented ESL spiking neural network is significantly more hardware-efficient than a traditional spiking neural network. Finally, potential applications for the ESL spiking neural network are discussed.