This paper proposes an external frequency synchronization control circuit for DC-DC converters, in which the frequency synchronization pin (SYNC) is shared with the enable pin (EN),enhancing chip compactness and reducing cost. The chip’s enable state is not affected by the external clock signal. An internal phase-locked loop (PLL) ensures the continuity of the switching frequency variation, thereby avoiding output voltage overshoot caused by abrupt frequency changes. The chip supports a frequency synchronization ranging from 200 kHz to 2.4 MHz and is implemented using SK hynix’s 0.18 μm BCD process. Test results show that the maximum output voltage overshoot is 58 mV with a 1 A load current and 1 MHz synchronization.

A practical copper-tape-based impedance matching circuit for helical antennas is presented, utilizing a Klopfenstein taper. The design uses standard acrylic cylinders and adhesive copper tape for low-cost fabrication without complex internal structures. The antenna achieves S₁₁ < -10 dB from 3.8 to 6.4 GHz, covering the 5.65-5.85 GHz range, with stable reflection coefficient characteristics. The insertion loss of the matching section was experimentally evaluated using a two-antenna method based on the Friis transmission equation, and was found to be less than 0.15 dB per matching section in the target operating band. This approach demonstrates a reproducible and low-loss matching technique suitable for microwave axial-mode helical antennas.

In this letter, an optimal switching pattern-based asymmetric three-phase decoupled modulation strategy for six-phase inverter-fed dual three-phase PMSM drive is proposed to improve the steady-state performance, as well as maintain a low switching frequency. Therein, the equivalent voltage vectors for the decoupled voltage vectors in harmonic plane are established. An optimal switching pattern for asymmetric three-phase modulation strategy considering current harmonic suppression is proposed. Comparative studies are conducted to demonstrate the effectiveness of the proposed modulation strategy.

This paper presents an 8-bit, 2-GS/s, time-interleaved analog-to-digital converter (TI-ADC) for communication systems. Featuring self-calibrating dynamic comparators in the sub-SAR ADCs to minimize offset and improve overall linearity. It breaks through the limitation that the offset calibration of traditional comparators tends to introduce quiescent power consumption. A circuit and layout for the TI-ADC have been designed in 40 nm CMOS. Operating at a 1-V supply voltage and 2-GHz clock frequency with a Nyquist frequency input, the design achieves a SNDR improvement from 42.11 dB to 47.11 dB, and a SFDR improvement from 60.46 dB to 63.64 dB. The power consumption is 25.79 mW.

In Systems-on-Chips (SoCs), logic locking is a vital technique for protecting Intellectual Property (IP) cores from leakage. Existing logic locking schemes based on Homomorphic Encryption (HE) employ a serial-blocking architecture, embedding high-latency cryptographic modules into the processor’s data path. This approach incurs significant performance overhead and limits the achievable security level. To address this bottleneck, this paper presents Homomorphic Feedback Locking (HFL), an architecture that decouples HE operations from the CPU’s execution path into a parallel, non-blocking feedback loop accessed via Control and Status Registers. We implemented HFL in a RISC-V SoC, characterized the privilege escalation event intervals under a system call workload, and developed a queuing model to analyze its performance overhead. Experimental results show that HFL with 83-bit security incurs a System Call performance overhead of only 15.0%, an improvement over the 33.5% overhead of a 41-bit serial-blocking scheme. Our model predicts performance scaling, explaining the overhead as a function of cryptographic workload and event arrival rate.

This study proposes a topology optimization approach to reduce current imbalance in a power module with multi parallel-connected devices. In this study, the conductor layout is derived by a density-based topology optimization that minimizes the coefficient of variation (CV) of the device currents under constraints for grayscale suppression, open/short-circuit prevention, and preservation of the total current. In the optimized results with 12 parallel devices, several disconnections occurred when open/short circuit prevention and the binarization term were not applied. By incorporating both methods, the optimized layout maintained proper connection and reduced current imbalance.

Data-retention flip-flop (DRFF) efficiently maintains data during sleep mode and retains state during transitions between active and sleep mode. This paper proposes a novel source-biased stacked inverter (SBS-Inverter) and a low-leakage, structure-reused DRFF. The sleep latch circuit constructed using the SBS-Inverter can effectively reduce the power of DRFF when storing data. Reuse of the structure improves the situation of redundant transistors in certain DRFF. Fine-grained inverter level optimization reduces delay and power during the active mode. The DRFF was implemented using a 55 nm process and subjected to comprehensive analysis. Post-layout simulation results at a supply voltage of 0.4 V indicate that the proposed DRFF’s data retention leakage power is only 5.3 pW. At a supply voltage of 0.8 V, the power-delay product is only 0.146 nW*ns@20 MHz. Monte Carlo simulation results considering process, voltage and temperature (PVT) variations show that the proposed DRFF can operate reliably down to a supply voltage of 0.4 V.

This work presents HiTAN, a hierarchical reverse modeling framework for automated analog IC sizing. Unlike conventional forward modeling, HiTAN directly infers design parameters from target performance specifications through an automated simulation-preprocessing pipeline combined with a lightweight multi-task attention mechanism. Validation on two representative LDO topologies demonstrates that HiTAN achieves high prediction accuracy, with an average parameter error below 2% and overall performance prediction accuracy exceeding 97%. Compared with baseline models, HiTAN consistently reduces design errors by a significant margin and generates parameter sets that satisfy multi-dimensional performance constraints, thereby enhancing circuit stability, efficiency, and robustness. These results confirm that reverse modeling not only accelerates the analog design process by reducing simulation overhead but also improves design quality and scalability for complex analog IC tasks.

Compared with single-edge designs, dual-edge-triggered flip-flops (DETFFs) can maintain the same data throughput while operating at half the clock frequency. However, when integrating ferroelectric nonvolatile structures with selector-based DETFFs, the uncertain logic levels of the clock and data signals during the restore phase may lead to unintended ferroelectric field-effect transistor (FeFET) programming. In addition, conventional C-element-based flip-flops suffer from limited performance. To address these issues, this paper presents an input C-element design that enforces input isolation by generating complementary outputs during the restore process, along with an improved output C-element. Experimental results show that, compared with existing C-element-based flip-flops, The proposed design reduces operating power by at least 33.3%, and decreases hold time by at least 58.8%. In addition, the clock-to-Q delay is reduced by at least 9.2%. The proposed flip-flop is capable of storing its output state prior to power-off and effectively isolating both data and clock signals during restoration, enabling accurate recovery of the pre-shutdown state while improving C-element performance.

Power consumption is a critical challenge in integrated circuit (IC) design. Since post-synthesis power simulation is time-consuming, fast and accurate pre-synthesis power estimation, especially at the register-transfer level (RTL) stage, is essential for guiding power optimization. However, existing RTL-stage power models struggle to simultaneously achieve cross-design generality and time-based resolution, and often rely on large-scale labeled training datasets. We present AtomPower, a general machine-learning (ML)-based power modeling framework for per-cycle power estimation across diverse RTL designs. AtomPower introduces the register structure tree (RST) to decompose a circuit into a fine-grained, bit-level structural representation, enabling accurate time-based power modeling. To address multicollinearity in regression and derive reliable power labels, we develop a finite greedy clustering (FGC) algorithm that specializes conventional clustering methods by incorporating structural constraints. In addition, we propose a tailored data augmentation strategy to significantly reduce the reliance on large labeled datasets during training. Evaluated on a diverse set of designs, AtomPower achieves a Mean Absolute Percentage Error (MAPE) of 5.02% and a correlation coefficient (R) of 0.85, outperforming state-of-the-art RTL-stage power models in both estimation accuracy and data efficiency.

Finite field inversion is a fundamental operation in cryptographic systems, particularly in Elliptic Curve Cryptography (ECC). The Itoh-Tsujii Algorithm (ITA) is a prevalent method for efficient inversion in hardware implementations within binary extension fields. This paper introduces an optimized parallel architecture for ITA that reduces computation time by minimizing clock cycles while maintaining a balanced trade-off in delay and area utilization. Our approach leverages a Hex-ITA framework in GF(2²³³), integrating Hex and Hex-root operations in parallel to enhance efficiency. The proposed design achieves a new benchmark in performance over existing designs. Experimental findings validate the scalability and performance of the proposed architecture, establishing it as a reliable choice for ECC-based cryptographic solutions.

This brief presents an ultra-low voltage (ULV) charge pump (CP) topology with high power conversion efficiency (PCE) designed for ultra-low supply voltage, low-power on-chip applications. The proposed ULV-CP employs a combination of dynamic gate-bias (DGB) and forward body-bias (FBB) techniques with the objective of enhancing overdrive voltage and reducing conduction losses, thereby enabling operation at ultra-low voltage. A 4-stage ULV-CP has been designed and implemented in a 22-nm FD-SOI process. Measurement result shows that it can reach a peak PCE of 83.87% at a supply voltage of 0.36 V. Compared to other CP circuits, the proposed circuit outperforms in terms of PCE, maximum output power, and minimum supply voltage.

In this letter, a 38 GHz asymmetric Doherty power amplifier (PA) that utilizes common-source (CS) amplifiers with different gate widths for the main and auxiliary PAs to align their optimal load impedances. Both the input quadrature hybrid network (QHN), output power combiner and inter stage matching network are designed by transformer-based structure. Furthermore, a quarter-wavelength impedance inverter is integrated into the output power combiner using a π-type C-L-C network, resulting in a more compact topology. The proposed Doherty PA, implemented in 65-nm CMOS process with a compact core area of 0.6×0.42 mm². At 38 GHz, the measured saturated output power (P_sat), 1-dB output compression point (OP1dB) and peak power added efficiency (PAE) are 19.7 dBm, 19.2 dBm and 25.4%, respectively. The measured PAE at 6-dB power back-off (PBO) is 19.1%.

Offset broadside coupled lines are widely used in directional couplers and quadrature hybrids. Ideally, these lines can achieve good isolation characteristics, but in the case of multi-section lines, the characteristics deteriorate due to the effect of junction discontinuities between lines. We propose a novel equivalent circuit model of junction discontinuities and a method for extracting equivalent circuit constants to understand this effect and design a compensating structure accurately. Using this proposed method, we modeled a multi-section quadrature hybrid coupler. We constructed a circuit model of the multi-section quadrature hybrid that agrees well with the results of full-wave electromagnetic (EM) simulations. This method enables simple and efficient structural design of complex circuit structures with multi-section coupled lines that require several hours or more for EM simulation.

This study applies a topology optimization approach to the design of a Junction Termination Extension (JTE), which is one of the edge-termination structures for vertical GaN power devices. Conventional parameter optimization requires independent tuning of the width, depth, and impurity concentration of the JTE region to achieve the desired breakdown voltage. As the number of target regions increases, the combinations of design parameters grow explosively. Consequently, severe constraints such as enforcing identical impurity concentrations across regions are often imposed, which substantially limit the design freedom. Focusing on the fact that a JTE structure can be represented as a dose distribution, we perform optimization with high design freedom using topology optimization. Since breakdown voltage correlates with the maximum electric field strength under reverse bias, we optimize the dose distribution to reduce the maximum electric field strength of the device. For a vertical GaN device biased at 900 V in reverse, the proposed method reduces the maximum electric field strength by 12.5% compared with a structure obtained by parameter optimization.