In recent years, fractional calculus has been used as a novel modeling tool by many converters. This paper studies the modeling of a pseudo-continuous conduction Buck-Boost converter based on the R-L fractional definition and the state-space averaging method. The expressions of DC static operating point, small signal transfer function and inductor current ripple are derived. It is found that compared with the Caputo fractional-order, the DC static operating point of the R-L fractional-order is not only related to the duty cycle, but also affected by the inductance and capacitance order and load. Finally, a fractional order model of PCCM Buck-Boost converter is built to verify the accuracy of the model. The results show that the fractional-order model can describe the operating characteristics of the Buck-Boost converter more accurately.

This article aims to improve the simplicity, speed, and accuracy of the resonance frequency identification algorithm. First, a brief introduction to the resonance of magnetic-geared motors (MGM) is provided. Then, a simple and more easily implementable identification method combining the second order generalized integrator and frequency locked loop (SOGI-FLL) is introduced. Based on this, to reduce convergence time and increase control degrees of freedom, an improved second order generalized integrator-frequency locked loop (ISOGI-FLL) identification algorithm is proposed, and its performance is analyzed. Finally, the effectiveness of the proposed algorithm is validated through experiments.

This paper proposes a high-sensitivity G-band detector module based on zero-bias Schottky diodes for direct detection radiometer receivers. To achieve a compact inline configuration with superior performance, the design features a novel U-shaped reduced-height waveguide transition, a cascaded CMRC low-pass filter, and an optimized DC grounding structure. Following rigorous EM-circuit co-simulations, the fabricated module was experimentally characterized. Measurement results demonstrate that the detector achieves a peak voltage responsivity of 9400 V/W in the small-signal regime. Specifically, at the target center frequency of 166 GHz, a high responsivity of approximately 6000 V/W is realized. The detector also exhibits excellent linearity (R² > 0.998) and flatness, validating its suitability for high-performance millimeter-wave sensing applications.

The efficient physical memory allocation is essential for high performance, particularly in architectures that support translation look-aside buffer (TLB) coalescing. The binary buddy system (BBS) is a widely used page allocator that operates in the block level. However, it enforces rigid power-of-2 block size constraints. This constraint undesirably incurs memory fragmentation and can degrade the memory system performance. To resolve this issue, we propose an architecture-specific allocator, namely a page-table level aware buddy system (LBS). Considering modern embedded system on a chip (SoC), where input/output (I/O) devices run high-bandwidth 2D data applications, we present the algorithm, an analysis, and performance experiments. The experiments indicate that, by integrating TLB coalescing, LBS can significantly reduce fragmentation and improve memory system performance.

In this letter, a novel matching network (MN) is proposed for the design of dual-band high-efficiency power amplifiers (PAs). The proposed MN consists of a compact harmonic control network and a fundamental MN integrating series two-section transmission lines, wherein multiple free parameters are introduced to improve design flexibility and expand the parameter solution space. The impedance transformation relationships are analyzed in detail, and explicit design formulas are given for directly solving the circuit parameters. The performance of the fundamental MN is also demonstrated and compared under varying complex load impedances and frequency-ratios. For verification, a 10 W GaN dual-band PA is designed. The measurement results show that the fabricated PA achieves drain efficiencies of 60.5%-73.7% within the 2.05-2.30 GHz band and 65.6%-76.8% within the 3.35-3.75 GHz band. A saturated output power of over 40.3 dBm is achieved in both operating bands.

This paper presents a high Common Mode Transient Immunity (CMTI) modulation circuit for a capacitively coupled gate driver. It proposes an enhanced on-off keying (OOK) transmitter architecture with integrated common-mode (CM) substrate modulation. Through collaboration with the CM interference detection circuit, transmission accuracy and CMTI are improved without additional delay. Test results show the prototype driver achieves 220 V/ns CMTI, 20 ns propagation delay, the rise and fall times of 10 ns and 12 ns respectively under 15 V supply voltage, and the rise and fall time of 22 ns and 24 ns respectively under 30 V supply voltage with 2.5 MHz frequency and 3.5 nF load.

This paper presents an autonomous bias-flip rectifier (BFR) integrated with an on-chip flip switch timing controller (FSTC) designed for piezoelectric energy harvesting. The proposed FSTC utilizes a pulse-width modulation (PWM)-based feedback loop that automatically calibrates the switch control pulse width, thereby eliminating the need for post-fabrication trimming and allowing the circuit to adapt to component variations. Implemented in a 0.18-μm CMOS process, the circuit achieves fully autonomous operation and can successfully cold-start from a piezoelectric harvester’s open-circuit voltage of 2 V. Measurement results confirm that the FSTC effectively optimizes the bias-flip timing, thereby maximizing the harvested power. Compared to an ideal full-bridge rectifier (FBR), the proposed BFR achieves up to 3.2× higher output power. These results demonstrate the effectiveness of the proposed on-chip automatic calibration architecture in realizing high-efficiency and cost-effective vibration energy harvesting systems.

In this letter, a 0.2-20 GHz ultra-wideband low-noise amplifier is proposed and fabricated using a 0.15-μm E-mode GaAs pHEMT process. To achieve high performance across ultra-wide bandwidths, we innovatively propose a design methodology that systematically integrates parasitic parameters as core design variables. Based on the methodology, a negative feedback topology along with an ultra-wideband decoupling network is designed and have been implemented. The fabricated chip exhibits a gain of 15.6 dB across the 0.2-20 GHz range with a gain ripple of ±0.6 dB and a noise figure below 1.86 dB. S₁₁ and S₂₂ are better than -12 dB and -8 dB, respectively. The proposed LNA also achieves an OP_1 dB of 17 dBm and an IP_1 dB of 1.4 dBm under a power consumption of 400 mW. Additionally, the fabricated LNA occupies a chip area of only 1.5 × 1.0 mm², including all pads.

To address the challenge of real-time and accurate identification of mutual inductance and load parameters in LCL-LCL-type magnetically coupled wireless power transfer (MC-WPT) systems, this paper proposes a parameter identification method based on a Fully Connected Network (FCN). By establishing the electrical model of the LCL-LCL-type MC-WPT system and constructing a high-dimensional simulation dataset, the FCN is utilized to achieve a high-precision nonlinear mapping between the system’s electrical quantities and the mutual inductance/load parameters. This method enables fast prediction and estimation of parameters, featuring advantages such as a simple structure, high computational efficiency, and ease of engineering implementation. Simulation and experimental results demonstrate that the proposed FCN identification model constrains the identification errors of mutual inductance and load parameters within 2.5%, while requiring minimal computational resources and achieving fast identification speed. The research findings can provide effective technical support for the online parameter identification of MC-WPT systems.

This paper presents a clock-skew-controlled pipeline optimization method for superconducting rapid single-flux-quantum (RSFQ) circuits. Without changing the circuit’s cell-level topology (netlist connectivity, including the splitter-tree), the pipeline depth along each signal path can be flexibly adjusted by controlling the clock skew between adjacent logic cells. A quantitative relationship between clock skew and latency variation is derived to determine timing configurations at different pipeline depths. A 4-bit adder is designed using cells from the SIMIT Nb03 process library, and a stepwise reduction of its pipeline depth is carried out in simulation to validate the method. At a fixed clock frequency and bias margin, the circuit latency is reduced by 155 ps, while the number of Josephson junctions (JJs) is reduced by about 582.

A novel single-stage lighting-emitting diode (LED) driver based on totem-pole bridgeless boost PFC rectifier and LCC resonant converter is proposed, the two units are integrated together by sharing switches. The totem-pole bridgeless boost PFC rectifier circuit operating in discontinuous conduction mode (DCM), which achieve high power factor. The LCC resonant converter is used here ensures that the primary side switches zero voltage switching (ZVS) and the secondary side diodes zero current switching (ZCS), which both reduce the number of semiconductors and increase the overall efficiency. Finally, a 100 W LED prototype is designed, fabricated, and test in the laboratory, the experimental results verify the theoretical prediction.

A high-frequency reference clock (CK_REF) adopted in charge-pump-based phase-locked loops (CPPLLs) can reduce the feedback division factor, thereby alleviating the noise influence from the phase/frequency detector (PFD), charge pump (CP), and loop filter (LF). However, the PFD, serving as the front end of CPPLLs, suffers from an enlarged blind zone (BZ) that consequently reduces its average gain (K_PFD) during high-frequency operation. To address this issue, this work proposes two pulsed-latch-based PFDs (PLPFDs) that mitigate the BZ and enhance K_PFD. Through analysis of the relationship between the clock frequency (f_CK), the reset loop delay, and the pulsewidth of the clock signal, these two PLPFDs can operate in either a higher-f_CK mode or a lower-BZ mode, depending on whether pulse generators (PGs) are used. Implemented using a 0.18-μm CMOS process, HSPICE simulation results demonstrate an operating frequency range of 1.8-3.4 GHz with lower power consumption in the higher-f_CK mode, and 0.5-1.7 GHz with a minimized BZ of 0.010-0.027 π in the lower-BZ mode. In particular, these PLPFDs can be readily integrated into CPPLLs that employ various high-frequency CK_REF, enabling fast acquisition for advanced communication systems.

A new permanent magnet linear generator (PMLG) for oscillating buoy wave energy converter (WEC) is proposed in this paper. Compared to traditional machines, this generator focuses on e enhancing the waveform and amplitude of the output voltage of wave energy generators. A detailed explanation of the operating principle, magnetic flux distribution, no-load characteristics, and load characteristics of the generator through analytical modeling and finite element analysis is provided. In the parametric analysis, the effects of different parameters on the no-load electromotive force are calculated to determine the optimal setting parameters. The simulation results demonstrate a significant improvement in the output voltage quality, expanding the effective operating range of the oscillating buoy-based power generation system and enhancing its efficiency. Moreover, by optimizing the input voltage, the design requirements for subsequent power conversion stages can be relaxed.

This paper proposes a cooperative strategy that combines virtual DC signal injection maximum torque per ampere (MTPA) with proportional-integral-resonant (PIR) control to mitigate the torque ripple of interior permanent magnet synchronous machines (IPMSMs) caused by inverter nonlinearity. The virtual DC signal is superimposed on the d-q-axis feedback currents to track the optimal current angle accurately, while a PIR controller provides high-gain compensation at the 5th and 7th harmonic frequencies, significantly improving current waveform quality. Experimental results demonstrate that, compared with conventional MTPA and MTPA with virtual signal injection only, the proposed scheme achieves the lowest torque ripple and total harmonic distortion (THD) of the phase current, and realizes higher-precision MTPA operation with a smaller current magnitude under identical load conditions.

This paper presents a background calibration technique that employs ramp signals with different slopes to simultaneously correct timing skew and buffer-induced harmonic distortion in time-interleaved analog-to-digital converters (TI-ADCs). During harmonic distortion calibration, a slow ramp is applied to the input buffer, and nonlinear coefficients are extracted from its transfer characteristics. These coefficients enable accurate digital-domain compensation without degrading the quality of the input signal. For skew calibration, a steep ramp is introduced to detect timing mismatches, providing an input-independent solution that imposes no constraints on the input signal. Furthermore, it avoids periodic variations in input impedance and prevents the generation of additional spurious tones. A 2.5-GS/s 12-bit TI-ADC behavioral model combined with transistor-level front-end circuits is developed to validate the proposed methods. Simulation results show significant improvements in SFDR across the entire frequency range, with skew-induced spurs effectively removed and harmonic distortion greatly suppressed.

In low-voltage differential signaling (LVDS) transmitters, data transfer between the core and I/O voltage domains across a large supply voltage difference requires high-speed and low-power level shifters (LSs). This paper proposes a level shifter (LS) that combines cross-coupled and improved current-mirror topologies to address the issues of current contention in the cross-coupled level shifter (CCLS) and limited swing in the current-mirror level shifter (CMLS). In the proposed LS, the improved CMLS branch employs an active-inductor structure and an auxiliary pull-up transistor to accelerate conversion, whereas current-limiting transistors inserted in the CCLS branch further reduce current contention. Implemented in a 55-nm technology, the proposed LS achieves 1.2 V-to-3.3 V level conversion at 800 MHz input frequency with a propagation delay of 249 ps and a dynamic power of 1.84 mW.

This paper presents a broadband inductor-less CMOS receiver architecture that eliminates on-chip inductors while maintaining wideband impedance matching and acceptable noise performance. The proposed receiver integrates an inductor-less low-noise amplifier (LNA) and an active mixer to achieve compact implementation and reduced parasitic sensitivity; the LNA employs a combined common-gate and common-source topology with a noise-cancellation scheme under a current-reuse configuration, and a modified Gilbert-cell mixer performs single-ended to differential conversion with controllable conversion gain without passive baluns. Designed in a 0.18-μm CMOS technology with a 1.8-V supply, post-layout simulation results demonstrate broadband operation from 0.4 to 2 GHz, achieving a conversion gain of 14.2-17.2 dB and a noise figure of 11.5-13.8 dB with the measurement buffer enabled, while the intrinsic front-end exhibits a minimum noise figure of 6.55 dB. The proposed architecture provides a practical trade-off among bandwidth, noise performance, linearity, and power consumption for highly integrated broadband RF front-end applications.