A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45 dB at 60 GHz, respectively.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency (f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181-f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

In this paper, an improved coverage optimization method for video sensor networks (VSNs) based on Whale optimization algorithm (SGWOA) is proposed to solve the problem of uneven distribution of nodes in random deployment of video sensor networks, which will cause coverage holes or coverage redundancy in the coverage area of VSNs. Firstly, Sobol sequence is used to initialize the population, which improves the diversity of the population and makes the distribution of network nodes more uniform when randomly deployed. Secondly, the nonlinear convergence factor and adaptive inertia weight are introduced to prevent the algorithm from falling into local optimal prematurely. Finally, Levi’s flight strategy is added to disturb the position update during whale optimization, which speeds up the convergence of the algorithm and avoids premature convergence.

This paper presents a transparent super-wideband (SWB) MIMO antenna based on a metal mesh structure. The metal patch and substrate of the antenna are hollowed out, resulting in a transparency of up to 77% and a radiation efficiency exceeding 82%. The bandwidth of this MIMO antenna ranges from 1.6 to 19.2 GHz, achieving a bandwidth ratio of 12:1. An engineered parasitic decoupling structure ensures that the isolation between antenna elements is greater than 25 dB, and the envelope correlation coefficient (ECC), diversity gain (DG), channel capacity loss (CCL), and total active reflection coefficient (TARC) all reach good values.

In this work, gate leakage behavior on Schottky-type p-GaN gate AlGaN/GaN HEMT is investigated, especially when the Schottky junction is damaged. A controllable degradation of the Schottky junction is achieved, then the previous semi-floated p-GaN is electrically connected to the gate electrode. Therefore, the pre-stressed GaN device exhibits an improved gate stability, as well as a normal gate control and large gate swing. Furthermore, the associated trap level is extracted by Arrhenius plot based on the exponential relationship between the recovery speed versus temperature.

In this paper, an Efficiency Optimization Strategy (EOS) is proposed to address the issue of low efficiency in the Dual Active Bridge (DAB) DC-DC converter across certain power ranges under wide voltage conditions, with the aim of further enhancing the converter’s efficiency over a broad operating range. First, in the low power range, a phase-shift control strategy is introduced, which enables wide-range Zero Voltage Switching (ZVS) and near-optimal inductor current RMS values. Through this strategy, ZVS is ensured for all switches under light load conditions, while under medium load conditions, ZVS is lost for only two switches. Subsequently, in the high power range, the optimization target is smoothly transitioned to the optimal RMS current value by utilizing the natural ZVS characteristics of the DAB converter. The operating range of the EOS is effectively extended, further reducing current stress and RMS current values, thereby achieving global efficiency optimization of the DAB converter. Finally, an experimental platform is constructed for verification, and the correctness and effectiveness of the theoretical analysis are confirmed by the experimental results.

Mel-frequency cepstral coefficients (MFCC), an FFT-based speech feature extraction (FEx) algorithm, is a significant power consumer in low-power keyword spotting (KWS) chips. This work presents a KWS chip with an energy-efficient FEx, with an expanded-3bit-twiddle FFT (E3bT-FFT) algorithm which reduces power of FFT by 5.7x. Meanwhile, a multiplier-free MFCC (MF-MFCC) is proposed, effectively eliminating power-hungry multipliers and reducing the MFCC computational load by 7.3x. Fabricated in a 65-nm CMOS process, the chip occupies 0.17 mm² and consumes 2.3 μW, with the computation unit in FEx consuming just 76 nW, and achieves 94.9% accuracy on a 1-Word KWS with Google Speech Commands dataset (GSCD).

In this paper, a smart system monitoring sensor based on a 12-bit SAR ADC with hybrid DAC is presented, and fabricated in a standard 55-nm CMOS process. By utilizing a MUX to switch the input channel, monitoring of the temperature and voltage at critical points is achieved. Additionally, a double conversion method is also proposed for circumventing the current mismatches of the two BJT temperature sensing elements, thereby lower the circuit complexity. For temperature sensing, the sensor shows a measured inaccuracy of ±1.5°C from -55°C to 125°C with an resolution of 0.86°C. For voltage sensing, the ADC shows a measured DNL and INL of +0.43/-0.47 LSB and +1.4/-1.1 LSB, respectively. Thanks to the proposed technique, the sensor consumes low power of 182 μW under a 1.8/1.2 V supply at a conversion speed of 156 kS/s, and occupies an area of 0.074 mm².

This paper reports p-channel metal-oxide heterostructure field-effect transistors (MOSHFETs) based on p-GaN/GaN/Al_0.29Ga_0.71N heterostructures grown by metal-organic chemical vapor epitaxy (MOCVD) on Si substrates. The two-dimensional hole gas (2DHG) density in the p-GaN/GaN/Al_0.29Ga_0.71N heterostructures is 1.3 × 10¹³ cm^-2 and remains unchanged down to a temperature of 80 K. A reduction of the GaN channel thickness by dry etching renders the p-channel MOSHFET enhancement-mode (E-mode) with a negative threshold voltage (V_th). The E-mode p-channel MOSHFET realized by GaN (18 nm)/Al_0.29Ga_0.71N shows a threshold voltage V_th of -0.79 V, an on-current |I_ON| of 2.41 mA/mm, a low off-state drain-source current (|I_OFF|) of 2.66 × 10^-9 mA/mm and a low subthreshold swing (SS) of 116 mV/dec. Such ultralow |I_OFF| and SS indicates high-quality epitaxial material. The high-temperature operation capability of the p-MOSHFET is evaluated up to 200°C.

CLLC converters are widely used in bidirectional DC applications, particularly in aviation and vehicle power supplies, requiring high dynamic commutation performance. This paper presents a commutation control method for CLLC converters based on a state trajectory model. The forward and reverse state trajectory models are developed, and the optimal commutation trajectory is derived. The gate drive signal’s pulse width is calculated based on the post-commutation gain. Simulations validate the proposed model’s accuracy and the control method’s dynamic performance, showing significant improvement over traditional linear control methods.

To meet the demands of 5G base stations in large PAPR signal environments, this paper presents the design of a 550 W improved three-stage Doherty power amplifier with a 12 dB back-off range. GaN HEMT devices with gate widths of 18 mm, 27 mm, and 27 mm are selected for internal matching design to ensure ultra-high output power. The paper analyzes the active load modulation mechanism under an asymmetric architecture and proposes an impedance matching design method suitable for this configuration. Test results in the 2.5-2.7 GHz show that the linear region gain is between 10.5 and 13.4 dB, the saturated output power ranges from 57.2 to 57.6 dBm, and the saturated drain efficiency is between 69% and 73%. At a 12 dB power back-off, the drain efficiency is between 55% and 58%. When the power back-off is 6 dB, the drain efficiency ranges from 62.2% to 65.1%. After incorporating Digital Pre-Distortion (DPD) technology, the ACPR test result is -55.9 dBc. These results address the issues of insufficient back-off range and linearity degradation due to saturation, which are common in traditional three-way and three-stage Doherty power amplifiers.

In low-voltage servo systems powered by batteries, as the battery continues to discharge and the system enters an under-voltage condition, the PMSM’s torque becomes limited due to the saturation of back electromotive force during motor startup. Additionally, in steady-state operation, the output torque is constrained. To address these issues, a novel control strategy is proposed that combines the Quasi-Z-source network with the low-voltage servo drive. The rate of change of the phase current amplitude of the PMSM is introduced as a compensation factor into the voltage loop control of the Quasi-Z-source network. This approach enhances the DC bus voltage and its dynamic response performance, thereby improving the motor’s output torque. Consequently, the proposed strategy effectively improves the system’s response speed and output capability under battery under-voltage conditions.

To address rare-earth dependency in PMSMs and low torque density in synchronous reluctance motors, a permanent magnet reluctance dual-rotor motor is proposed. A collaborative genetic algorithm optimizes a 7.5° magnetic bias angle and the parameter scanning method is employed, reducing cogging torque by 90.8% and torque ripple by 11.1%. A hierarchical control scheme uses hysteresis control for current loops, a torque distribution algorithm is introduced to address the coupling issue between the dual rotors, and adaptive sliding mode control for speed loops. The rotational speed overshoot is constrained within 2%, achieving 0.05 s response, and reducing chattering. Simulations validate the method.

In this paper, an AC-DC constant current buck converter is designed, and a novel high voltage self-powered method of chip is proposed. Through the VIN valley power supply technology, the serious problem of heating for integrated high voltage power supply of AC-DC converter is solved, and making high voltage integrated power supply of high power system possible. The chip is designed and produced in 0.18 μm UHVBCD process. A 50 W BUCK converter prototype with this chip as the core is developed. The test results show that the constant current performance is good, with the line regulation is 1.7%, and the load regulation is 3.2%. The chip temperature is lower than 110°C. The experimental results of prototype demonstrate the effectiveness of the proposed circuit. This design reduces peripheral devices, saves costs and improves the integration degree.

In this paper, a guiding conductive strip is proposed to provide EMI protection for small modular reactors based on digital technology. We employ the mode-matching method to analyze the decoupling performance of the proposed guiding conductive strip. Using the validated mode-matching method, we derive the optimal location of the guiding conductive strip to confine the undesired electromagnetic influence by using the capacitance matrix as the figure of merit. We also interpret the operating principle of the proposed guiding conductive strip by analyzing the electric field strength distribution. The performed mode matching analysis for the guiding conductive strip provides useful information to mitigate the electromagnetic interference in the modernized nuclear power plants, such as a small modular reactor.

In this paper, a flyback AC/DC converter without auxiliary windings, opto-couplers or output voltage feedback resistors is proposed. A novel method for detecting output voltage and output current was adopted. By detecting the voltage difference between the two ends of the primary winding, the secondary winding current and output voltage were detected. Peripheral devices have been saved, costs have been reduced, and the integration degree of the switching power supply system has been greatly improved. The chip was designed and produced under 0.18 um UHVBCD technology. A 22 W flyback converter with this chip as the core is developed. The test results show that the constant current characteristic is good, the line regulation is 1.4%, and the load regulation is 2.1%. The output over voltage protection function is good, with an accurate threshold: the line regulation is only 3.4% and the temperature coefficient is only 4.5%. The experimental results of prototype demonstrate the effectiveness of the proposed circuit.

A self-regulated bandgap voltage reference (BGR) circuit with high order temperature compensation is presented. The self-regulated structure reduces the reference voltage variation due to the changes of supply voltage and achieves good performance on power supply rejection (PSR). To improve temperature coefficient (TC) of reference voltage, high order temperature compensation is applied without using additional amplifier, which saves area and power consumption. Implemented in a 0.18 μm BCD 1P4M process, measured results show that the proposed BGR achieves a best TC of 2.7 ppm/°C from -40 to 125°C after trimming and a line sensitivity of 0.008%/V under a supply range from 2-5.5 V. The total circuit area is 0.0585 mm² with a current consumption of 37.5 μA.

Deep learning-based Design Rule Violation (DRV) prediction is increasingly applied in advanced integrated circuit design. In this paper, we present an optimized Convolutional Neural Network (CNN) model that incorporates two novel input features for improved prediction. Clustering degree feature and complex pin feature significantly enhance the model ability to extract layout information. Additionally, the optimized CNN model “RouteNet-AMK” improves processing capabilities for complex layout data by incorporating the attention mechanism and multi-scale feature fusion technique. Experimental results show that the F1 score of the proposed method on the CircuitNet N28 dataset is 2.94% higher than that of the RouteNet model using conventional features.

This paper presents a novel challenge selection methodology for delay-based physical unclonable functions (PUFs), which effectively balances the delay skew induced by asymmetric routing and enhances the uniformity of FPGA implementations. A mathematical delay model of PUF is established to analyze the asymmetry characteristics in FPGA architectures, including the routing discrepancies between delay elements and the non-equivalent signal paths within lookup table-based (LUT-based) delay elements. To mitigate the impact of non-ideal factors, a delay-balancing analysis approach is proposed to equalize the delays of asymmetric routing paths. A challenge selection algorithm is then developed to identify optimal symmetric paths based on the delay-balancing results. As proof of concept, six 64-bit arbiter PUFs (APUFs) are implemented to validate the proposed approach. Experimental results demonstrate that 25% of challenges are selected from a 16-bit challenge space, significantly improving the uniformity compared to the pre-selection approach.

Traditional LLC converters suffer from efficiency degradation and load-dependent voltage regulation when operating off-resonance for wide output ranges. This paper proposes a dual-mode secondary-side modulated LLC topology. The primary side switches between Dual Full-Bridge (DFB) and Dual Half-Bridge (DHB) modes, significantly widening the output voltage range. Simple secondary-side PWM modulation achieves load-independent regulation and maintains ZVS operation at the resonant frequency for high efficiency. A PI-BPNN smooth transition strategy is introduced to mitigate voltage overshoot during mode switching. A 195 V input, 48.75-390 V output prototype validates the converter’s advantages and the control strategy’s effectiveness.

This paper presents a control strategy to reduce current stress and reactive power in high-efficiency single-stage double-active-bridge (DAB) photovoltaic microinverters. It uses a changing ratio of the phase shift angle between the primary and secondary bridges to the phase shift angle inside the primary bridge, instead of a fixed value, to obtain better performance. First, variable frequency control is used to linearize the phase shift function. Then, the variation pattern of the phase-shift ratio is optimized through online calculation. This method expands the zero-voltage switching (ZVS) range, lowers current stress and reactive power, and achieves 96.68% efficiency in the DAB microinverter. Experiments on a 400-W prototype confirm the effectiveness of the method.

This article introduces a bandgap reference (BGR) circuit with high power supply rejection ratio and low temperature coefficient (TC). The circuit employs a self regulating technique to significantly suppress the supply noise. Furthermore,a curvature compensation structure is proposed to reduce the TC. The proposed BGR uses a 180 nm standard process. This design achieves an ultra-low temperature coefficient (TC) of 1.76 ppm/°C from -40°C to 125°C with a high PSRR of -112 dB at 10 KHz.

High-speed Field-Programmable Gate Array (FPGA) packet-processing typically relies on streaming buses such as AXI-Stream for their explicit packet semantics, but high-speed I/O blocks including 200-400 Gbps Ethernet MACs and PCIe IP cores expose segmented buses that deliver multiple fixed-width segments per cycle. This mismatch motivates the need for efficient streaming-segmented bus conversion. This letter presents a structured FPGA architecture for bidirectional conversion between streaming and segmented buses, and demonstrates a prototype on AXIS and Intel Segmented Client Interface. The design integrates a high-speed dual-buffer organization with a metadata-driven mechanism that extracts frame-boundary and sideband information early in the pipeline. By decoupling control signals from payload, the proposed architecture shortens the critical path of the extraction Finite State Machine (FSM), thereby achieving high-frequency performance. The prototype implementation on an Intel Agilex 7 FPGA achieves 400 Gbps throughput at 415 MHz on a 1024-bit bus for packets of 128 bytes and above, with less than 3% resource usage. The architecture is parameterizable and can be mapped to other streaming and segmented bus formats with minor interface adaptation.

This paper proposes a bandgap reference (BGR) voltage source with high power supply rejection ratio (PSRR), low temperature coefficient (TC), and high robustness for automotive chip electronic systems. To reduce the temperature coefficient and save chip area, a self-biased high-order temperature compensation technology is developed in the design. The proposed BGR is implemented based on 180 nm process, with an effective area of only 0.01 mm². Experimental results show that under a supply voltage of 3.3 V, it outputs a reference voltage of 1.2 V, with an average temperature coefficient as low as 2.2 ppm/°C, a PSRR of up to -120 dB at the DC operating point, and a process coefficient of variation (σ/μ) of only 0.06%, which can meet the application requirements of automotive chips for high - precision reference sources.

This paper presents a multi-step interpolation structure Time-to-Digital Converter (TDC) with a wide dynamic range, high resolution, and a robust anti-PVT mechanism. The architecture is based on a coarse counter, a middle-step interpolator implemented by a PLL, and a fine-step interpolator consisting of a multi-quadrant 2-D Vernier array. The coarse counter extends the TDC’s measurement range, while the middle-step interpolator, as a key component of the PVT calibration module, significantly reduces nonlinearities caused by process, voltage, and temperature (PVT) variations. The proposed multi-quadrant 2-D Vernier array doubles the measurement range of the fine-step interpolator, while maintaining the TDC’s resolution. The TDC was implemented in 180 nm standard CMOS technology, with a reference clock frequency of just 10 MHz, achieving a detection range exceeding 25 μs and a fine resolution of 5.36 ps. To further compare the nonlinearities of the proposed multi-quadrant 2-D Vernier array with the traditional 2-D Vernier wide range comparator array, an existing theoretical model is used to analyze the DNL and INL, and both of them exhibit significant advantages and an optimization of over 50% can be theoretically achieved.

A compact monopole antenna designed for triple-band functionality in multiple application networks is proposed. This antenna simply contains a pair of antisymmetric L-shaped branches and is constructed on FR4 substrate, which occupies only a miniature volume of 10 × 20 × 1.6 mm³. By properly designing the branches based on multiple harmonic resonance, three impedance bands including 2.35-2.7, 3.3-3.7, 5.05-9 GHz can be completed with this antenna. The antenna’s resonant characteristics can be easily adjusted by changing the lengths and widths of its branches. With a compacted size and suitable radiation performance, the suggested monopole antenna may well work as an internal antenna for LTE/Wlan/Wimax/5G NR/V2X/WiFi 7 band wireless applications.

This study investigates the radiation mechanism of magneto-electric (ME) dipole antennas through characteristic mode analysis (CMA). Two distinct resonance modes responsible for the formation of dual resonance points are identified. Furthermore, an analytical investigation on wide dipole antennas is performed, leading to the realization of a perfectly complementary radiation pattern with a maximum front-to-back ratio (FTBR) of 40.16 dB. The proposed theoretical framework is further validated through its implementation in ME dipole antennas with more complex structures at mmWave bands. This study innovatively advances the current theoretical framework and provides guidance for future design and optimization of ME antenna.

In this paper, we present the design and fabrication of a 1060-nm single-mode edge-emitting semiconductor laser based on an oxide-confined, surface-grating architecture that simultaneously enables lateral fundamental-mode control, robust longitudinal single-mode operation, and high efficiency with a regrowth-free process flow. Simulations confirm strong overlap of the fundamental mode with the oxide aperture and effective suppression of higher-order lateral modes, consistent with the measured narrow far-field. Under CW operation at room temperature, the device exhibits a low threshold current of 19 mA and a maximum slope efficiency of 0.7 W/A, and it maintains stable lasing at 85°C with a slope efficiency of 0.64 W/A. A low lateral divergence of 4.2° (FWHM) and a side-mode suppression ratio of 38 dB further demonstrate excellent beam quality and spectral purity.

This letter introduces a method to optimize the temperature offset drift and noise efficiency factor (NEF) for chopper and auto-zero instrumentation amplifiers. In order to optimize offset drift and NEF, our proposed amplifier exploits a threshold voltage (V_th) tracking reference. A prototype of the proposed amplifier was fabricated using a standard 0.35 μm complementary metal oxide semiconductor technology and occupies 0.174 mm². Using the Vth tracking reference, an offset drift of 80 nV/°C is achieved. The measured NEF was 2.45 with a supply current of 1.1 mA.

This paper presents a high-resolution second-order delta-sigma (ΔΣ) ADC in 22 nm FD-SOI technology. To overcome the trade-off between voltage headroom and linearity, a buffered dynamic body-Biased (BDBB) gate-bootstrapped switch is introduced. This structure decouples the input signal from the parasitic body capacitance, effectively suppressing harmonic distortion and minimizing aperture jitter. The modulator employs a cascaded integrator feed-forward (CIFF) architecture with gain-boosted op-amps, achieving a peak signal-to-noise and distortion ratio (SNDR) of 104.9 dB and an effective number of bits (ENOB) of 17.1 bits in a 10 kHz bandwidth. A digital decimation filter performs 640× downsampling to provide a 24-bit output. Operating at a 1.2 V supply and 12.8 MS/s sampling rate, the proposed design achieves an spurious-free dynamic range (SFDR) of over 100 dB, making it highly suitable for high-precision signal acquisition.