Thermal noise is one of the most important limiting factors on the performance of switched-capacitor (SC) circuit due to the aliasing effect of wide-band thermal noise. In this paper a new simple method for estimating the effect of thermal noise is presented. In the proposed technique only the discrete sampled noise is considered. HSPICE simulator and analytical analysis are used to estimate the sampled noise specification on each clock state. Next, using difference equations of the circuit, time domain simulation is done by MATLAB. Based on this method, a SC integrator is analyzed and results compared to the measured noise response.

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This paper presents a modified H-bridge seven-level single-phase grid-connected inverter for photovoltaic system with a novel pulse-width-modulated (PWM) control scheme. The inverter is capable of producing seven output-voltage levels (V_dc, 2V_dc/3, V_dc/3, 0, -V_dc, -2V_dc/3, -V_dc/3) from the dc supply voltage. Perturb and Observe (P&O) algorithm is used to extract maximum power from the PV module. MPPT and current control algorithm were implemented in an eZdsp board, TMS320F2812. The proposed system was implemented in a prototype.

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This paper describes a technique to improve the linearity of low noise amplifier (LNA) that is implemented by the shunt-shunt feedback (SSFB) topology. By employing a parallel positive/negative feedback a suppression of the 2nd order harmonic distortion (OHD) in the feedback loop can be achieved which will result in minimization of the IM3 that is produced by mixing of this 2nd OHD with the input signal leading to an improvement of the LNA IIP3. Two LNA were fabricated using 180nm CMOS technology one adopting the conventional SSFB that was described in [1] and another one using our proposed linearization technique where an average improvement of +8dBm of IIP3 is achieved while maintaining quite similar minimum noise figure of 2.8dB, 3-dB bandwidth of 3.7GHz. Each of the fabricated LNAs consumes a current of 7.8mA from 1.8V power supply and occupies 0.007mm².

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In this paper a low power fully differential current buffer is introduced which performs high CMRR exploiting a novel method to alleviate common mode gain. The proposed current buffer is designed and simulated with HSPICE in 0.18µm CMOS process and supply voltage of ±0.75V. The simulation results show an 8.48Ω input resistance, 98dB CMRR, 369MHz bandwidth and power dissipation of 135µW. The corner case simulation has been done which shows an acceptable performance for the proposed buffer in all situations. The proposed circuit tends to be the fundamental block of a new family of electronic differential topologies greatly capable to be much further improved and utilized.

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In this paper, we present a contents-based digital imageprotection technique using Cellular Automata Transforms (CAT). CAT has a huge number of combinations — gateway value — such as rule number, initial configuration, boundary condition and basis function type. CAT coefficients and digital image copyright are used to generate a new contents-based copyright message that will be stored in a database with CAT parameters. A possibility of copyright dispute will clearly show a copyright that is extracted from its received image and the saved contents-based copyright. The simulation results show that the proposed method is robust to attacks and is more secure than using the gray-scale contents-based method.

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This letter reports on the micro-patterning of the photosensitive protein of bacterioRhodopsin (bR) geared toward bioelectronics-based image sensors. bR proteins are denatured by existing micro-fabrication processes, including destructive high-temperature (>100°C) heating and organic solvent cleansing. In our process, the desired area of the electrode for immobilizing bR is defined by a hydrophobic polymer that repels bR. After micro-fabrication, bR is selectively formed on the defined areas using electrophoretic deposition. A 5-µ m patterning resolution was achieved. An 8 × 8 photosensor array was fabricated, and its output electric charge was detected.

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For resonator-coupled wireless power transfer systems, various kinds of coil resonators are studied experimentally. First, it should be noted that those systems are explained by a two-pole bandpass filter model with electromagnetic coupling between resonators. Then transfer loss is estimated explicitly. Three kinds of coil resonators are compared quantitatively, a spiral coil, an edge-wise spiral coil, and a solenoidal coil. Unloaded Q, external Q, and coupling coefficient k are measured by experiments. Among them, the spiral coil is found to be suitable for the wireless power transfer. Simulation result shows good agreement with the experimental result and is supported with the experimental result. As a result, it is confirmed that the power transfer system can be designed by the conventional multi-stage filter theory. And the advantage of spiral coil is shown.

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A new NoC (network on chip) architecture using lossless data compression and decompression to improve the performance and power efficiency of the on-chip interconnect is proposed. In the proposed NoC scheme, the sender compresses the data to be transferred in order to reduce the number of data packets and the receiver decompresses the encoded data to restore the original data. For the lossless compression and decompression, we have implemented a hardware CODEC based on a Golomb-Rice algorithm. According to the experimental results using a cycle-accurate NoC simulator, the proposed scheme could significantly improve the performance and power efficiency of the conventional NoC architecture.

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An unmatched source synchronous I/O link is proposed to reduce the time jitter of the sampling clocks for a receiver (RX) in a chip-to-chip interface system using a multi-phase clock. The proposed I/O link is initialized by two consecutive phase lock processes to optimize the RX sampling clocks. In the coarse lock process, the phase of the transmitted clock for a source synchronous I/O link is controlled by the resolution of the unit internal in the transmitter (TX) chip. The feedback path from the RX chip to the TX chip for the coarse lock information is merged into the normal path. The fine lock process is executed by a phase interpolator in the RX chip. The proposed I/O link reduces the latency and time jitter of RX sampling clocks by achieving the coarse lock process in the TX chip. To verify the proposed I/O link, a transceiver for a source synchronous I/O link clock with a quad data rate scheme was designed by using a 70nm DRAM process with a 1.5V supply. The proposed I/O link reduced the maximum jitter noise value by 42.4% in comparison to the jitter noise of a conventional multi-phase clock scheme.

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Flash translation layer (FTL) is generally used for NAND flash memory in order to handle the mapping between logical page address and physical page address. Log buffer-based FTLs provide good performances with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping architecture between data block and log block, called associativity. While previous static schemes use fixed associativities, our scheme adjusts the associativity dynamically based on the run-time workload variation improving the performance by 5∼16% compared to the static scheme.

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A novel measurement method of material parameters for uniaxially anisotropic artificial dielectrics is proposed. The method utilizes the transmission characteristics with a waveguide. This method is valid for the artificial dielectrics where the size of constituting particles is negligibly small compared with the wavelength, and the frequency dependency of the material parameters is very small. Our method requires only one piece of sample for measurement. In the case where the test piece of the material is thin enough, the material parameters can be calculated analytically. The theoretical considerations are confirmed by the experiments for artificial dielectrics.

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A high-speed DQPSK optical modulator is fabricated with a thin lithium niobate substrate. Decrease in the propagation loss of electrodes and a low half-wave voltage, which can be realized by fabrication of a ridge-type optical waveguide structure, can help achieve 120-Gb/s (60-Gbaud) NRZ-DQPSK modulation with full electrical-time-division-multiplexing technique.

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We have successfully demonstrated an AWG with a wide and rectangular passband by introducing a new concept using 0th and 1st order modes. An interference circuit consisting of a tandem MZI and a mode converter at the entrance of the 1st slab waveguide perturbs the input light field, thus attaining a 0.5-dB bandwidth of 69% relative to its channel spacing.

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