A 5.7GHz low noise ultra high gain CMOS LNA with inter stage technique is presented in this paper. The noise and gain performance is improved using common-source transistor inter stage network. A bias resistor of large value is placed between source and the body node to prevent body effect and reduce noise. The simulated 0.18µm CMOS LNA achieves -14dB and -17.5dB input and output return loss respectively. Compared to previously published current-reused LNA, the proposed LNA has the smallest noise figure of 1.85dB, extremely high gain 32.5dB, and the highest Figure of Merit of 87.28.

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In this paper a new structure for comparator-based switched-capacitor circuits has been presented. In contrast with the conventional architecture the proposed algorithm utilizes an extra comparator to make a variable comparator threshold, in order to attenuating the overshoot at the end of the coarse phase. for better designing we introduced some practical issues on preset levels designing. After that this paper proposes a feed forward offset compensation which can avoid offset accumulation in proposed architectures. Finally we designed a 10b 20MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 74.4-dB spurious-free-dynamic range (SFDR) and 58.34-dB SNDR. In addition It consumes 2.6mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 210fJ/step.

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This paper proposes a lossless data hiding method which accepts various payload sizes. A lossless data hiding method once distorts an image to embed data into the image. From the distorted image, the method extracts the inserted payload data and restores the original image. The proposed method does not have to memorize any parameter for data extraction and image recovery. By simple modification to the conventional method having the above mentioned features, the proposed method becomes free from fixing payload size and from iterative parameter estimation.

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A wide range digital leakage current mismatch compensator for a short-channel charge pump (CP) circuit is presented. Equipped with leakage current generators and leakage current mirrors, the proposed leakage current mismatch compensator can reduce the PMOS and NMOS leakage current mismatch to less than 1/10 times of its initial value for wide range of leakage current mismatches. For simulation, a CP circuit with the proposed leakage current mismatch compensator was designed in a 0.13µm 1P8M CMOS process.

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In this paper a fully differential comparator-based switched-capacitor (CBSC) pipelined ADC is presented. For better performance and accuracy, we modified the differential architecture and introduced some practical issues on preset levels designing. For comparison, we used a simple comparator which can compensate offset easily. Finally we designed a 12b 40MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 75.2-dB spurious-free-dynamic range (SFDR) and 69.78-dB SNDR. In addition it consumes 4.1mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 460fJ/step.

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Power Amplifiers (PAs) are important parts of the transmitters. They amplify the signals that are going to be transmitted. With increasing the input power of the PA, it creates the nonlinearity at the output. The nonlinearity causes out of band distortion and in band distortion. To overcome these effects the power amplifier should be backed off but it will reduce the efficiency of the PA. To increase the efficiency, the Complex Gain Memory Predistortion (CGP) is added to the system. Experimental results with the Mini Circuit power amplifier show an improvement of 7% in Power Added Efficiency (PAE) when the CGP method is applied.

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We propose a novel method to efficiently correct the aberration in a free-space optical switch, where a spatial light modulator (SLM) is used to control wavefronts. A particle swarm optimization (PSO) method is applied to finding the optimum set of Zernike modes to compensate the aberration. We find out that the obtained coefficients of the lower-order modes and those of the higher-order ones exhibit a linear relationship when the optimization flow is interrupted by the local optima. We can drastically reduce the time for the calibration by using this relationship among the Zernike coefficients.

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The RFID tags are used for low cost and convenient object identification. For the fast tag identification, the anti-collision algorithm is used. A new algorithm to identify RFID tags using a shortened ID instead of a long original tag ID is proposed. The proposed method changes the length of the shortened ID adaptively according to the number of unidentified tags. The proposed algorithm shows better performance compared to previous anti-collision algorithms in terms of average transmitted bits per one tag identification.

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This paper presents a digital background calibration technique to correct the capacitors mismatch, gain error and gain nonlinearities of 1.5bit/stage pipelined ADCs. The calibration technique uses a modified structure for the ADC stages, the skip-fill method and LMS algorithm and does not require any accurate calibration signal and any added analog circuitry; just some digital circuits are needed to fill the skipped samples and realize the LMS algorithm. Circuit level simulation results in a 90-nm CMOS technology are provided for a 12-bit 80-MS/s pipelined ADC to verify the effectiveness of the proposed calibration technique.

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In this paper, a robust carrier frequency offset (CFO) estimation scheme is proposed for OFDM systems in Doppler shift channels. We first present a training symbol (TS) pattern that has the same value so as to provide a wide CFO estimation range and to ensure the accuracy of the CFO estimation. Using the TS, we then present maximum-Likelihood (ML) and averaging least square (LS) algorithms for performing acquisition and tracking steps of the CFO estimation. The performance of the proposed technique is evaluated with respect to a mean-square-error (MSE) and a bit-error-rate (BER) in a typical urban (TU) channel.

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This paper presents a low-energy prime-field elliptic-curve cryptography (ECC) hardware processor, suitable for low-power and/or energy-efficient applications and systems. The ECC processor is obtained by power-optimizing a previously reported design. The optimization is performed by making the power consumption profile of the processor as uniform as possible, in an attempt to increase the secondary battery life between discharge and recharge cycles and to create resistance against simple power attacks (SPA) to the cryptosystem by analyzing the power dissipation trace of the hardware. The optimized ECC processor performs a single 192-bit scalar multiplication in 652ms consuming only 22.3µJ at a clock frequency of 1MHz. This indicates, in addition to the more uniform power consumption, a 13% reduction in the energy and power consumption compared to the previously reported design.

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A numerical simulation of gain measurement performed using the three-antenna method for a log-periodic dipole array antenna (LPDA) is presented. The electromagnetic simulation is based on the finite integration method. The gain variation attributable to measurement distance is estimated when using the conventional method in which the reference point of LPDA is considered. We propose a technique for estimating the phase center by exploiting this gain variation. The simulated results demonstrate the efficacy of considering the phase center for accurate antenna calibration.

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