In this paper, we propose a hardware oriented vector quantization algorithm employing rough-winner-take-all neural network. The proposed algorithm is almost same as K-means clustering which is the simplest vector quantization. The only different point is that the proposed method employs rough-winner-take-all as the substitute of ordinary winner-take-all. In a rough-winner-take-all strategy, the winner is roughly selected in the early learning stage and is strictly assigned in the later stage. The simulation results show that the quantization performance of the proposed method is nearly equal to Neural Gas which is an excellent vector quantization. Besides, the proposed method can be realized as an extra mode of existing K-means or Self-Organizing Map hardware by changing its winner-take-all controlling.

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This paper describes a design procedure for mm-wave voltage controlled oscillator (VCO), based on large signal behavior of oscillator transconductance. Then, a new structure of LC-VCO is presented, which utilizes a transformer feedback to enhance the transconductance of the core transistors and to cancel the undesired parasitic effects. Using a 0.18-µm RF CMOS technology, the advantage of this VCO is examined by large signal analysis and simulation. The results illustrate improvement of 5dB in phase-noise and 70% in tuning-range, compared to enhanced active gain conventional transformer feedback VCO. Finally, a compact layout for transformer design is proposed.

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External memory access exacts considerable timing and energy burdens from portable devices. However, most hardware accelerators for rendering two-dimensional (2D) vector graphics draw images in a path-based (path-by-path) manner, which frequently causes excessive external memory traffic. This paper proposes a scanline-based method for rendering 2D vector graphics in portable devices. The proposed method processes all paths spanning a scanline at a time, enabling the use of a scanline-sized internal frame buffer (FB). Using the internal FB, the accelerator can avoid repeated accesses to the external FB and reduce external memory access considerably for images in which many objects overlap with one another.

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In this paper, we propose a new time synchronization method for femtocells connected to the core network through IEEE 802.11 based wireless link. In the proposed method, the time information is transmitted to a femtocell via the wireless backhaul using modified IEEE 802.11 beacon frames, and a least squared based estimation method is used to reduce the timing jitter at the femtocell. Through simulations, it is shown that the femtocells using the proposed algorithm satisfy the time accuracy specification for M-WiMAX.

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We investigated the dynamics of fiber fuse propagation with a long-period damage track and its power dependence in hole-assisted fiber. When the input power is high, the fiber fuse velocity changes greatly over the propagation distance. However, when the input power is low, the velocity change is small and the fiber fuse propagates in almost the same way as in a conventional single-mode fiber. We found that the fiber fuse propagation becomes unstable when the input power exceeds 4.7W at a wavelength of 1550nm.

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In this paper, defected ground structures have been implemented in order to obtain effective size reduction and harmonic suppression in dual-frequency Wilkinson power divider (WPD). At first, a dumbbell DGS is applied into dual-frequency WPD and both operating frequencies have been decreased as half as the previous ones. Therefore, 49% size reduction has been achieved. Second, by using spiral DGS, suppression for the second and third harmonics are achieved. Second harmonic of first operating frequency is suppressed by -21dB. Second and third harmonics of second operating frequency are suppressed by -37dB. There is a good agreement between simulated and measured results.

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Most of the commercially available vector network analyzers have a high pass cut-off frequency in the higher kHz-range. One of the main reasons is the frequency limitation of the directional device used. In this paper, a simple directional bridge circuit with incorporated frequency conversion stage is presented. This DC-coupled circuit enables vector network analyzer receiver front-ends to work near DC, expanding the frequency range by several decades. The directivity is similar to these of directional bridges used in commercially available analyzers, but this in a frequency range down to DC.

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A novel non-coherent binary phase shift keying (BPSK) demodulator featuring ultra-low power and high data rate is presented for inductively powered biomedical implants. A self-calibration technique with process variations compensation is proposed in order to minimize the effect of transmitter frequency changes and to enhance circuit robustness. The circuit is designed in the 0.18µm standard CMOS technology. Simulation results show that the demodulator can tolerate a relatively large frequency shift of at least 85% around the centre frequency in all process corners. The power consumption of the demodulator at a data transmission rate of 16Mbps is as low as 9.4µW at a supply voltage of 1.8V, which is much lower compared to other state of the art BPSK demodulators.

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A 2.4-GHz CMOS on-off keying (OOK) transmitter is developed for applications that require high data rate over 10Mbps in the area of wireless body area network (WBAN) and medical implant communication service (MICS). A novel analog pulse-shaping circuit for reducing power consumption and circuit complexity is employed for the OOK transmitter. Fabricated in 0.13µm CMOS, the transmitter core excluding the 50 ohm driving buffer dissipates 0.95mW from 1.2-V supply. Measurement shows that it can support the data rate up to 22Mbps. With the pulse-shaping capability enabled, the transmitter output spectrum shows successful suppression of the sidelobe power below -42dBc at 100MHz offset from the center frequency.

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In this paper, a 120mV input startup circuit based on novel charge pump architecture is proposed. The startup circuit can boost input voltages ranging from 120mV to 300mV while supplying voltages 280mV to 1.6V at the output with approximately 23% efficiency. To verify the circuit behavior, the test circuit has been implemented using 0.18µm CMOS process. The low voltage, low area startup circuit is suitable for ultra low voltage applications such as energy harvesters and allows for single chip integration.

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This paper proposed a novel index board rasterization architecture which reduces mathematical calculations and memory traffic for vector graphics. The proposed architecture uses the cell based method which has advantages in computational complexity, and generates the active span by referring to only valid cells and placing them in scanline order with two internal SRAMs. The proposed architecture reduces the amount of calculation by an average of 59.4% and also the external memory traffic by an average of 30.0% compared to the traditional architecture.

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In this paper, a pulse width modulation (PWM) generator based on a switched capacitor for LCD backlight brightness control is described. The proposed scheme uses a simple RC network along with a clocked-comparator which samples the output of the ambient light sensor, and generates a PWM signal corresponding to the light level. Furthermore, by using a switched-capacitor resistor with variable clock frequency, the RC time constant is programmable and less sensitive to process variations with respect to passive resistors. In addition, it is shown that the linearity of the proposed PWM generator can be enhanced by replacing the RC network resistor with a constant current source. The operation of the PWM generator is verified through circuit level simulations, and the prototype circuit is fabricated using CMOS 0.18um technology.

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A multilayer diplexer in a low temperature co-fired ceramic substrate for compact ultra-wideband (UWB) wireless modules is presented. This diplexer can separate the band group 1 (3.168-4.752GHz) of multiband orthogonal frequency-division multiplexing UWB systems from the band groups 3 and 4 (6.336-9.504GHz) of the same systems. The basic characteristics of the diplexer are simulated with a circuit simulator and an electromagnetic simulator. The fabrication and measurement of the presented diplexer are also carried out. The measured results of the fabricated diplexer agree well with the simulated results. The insertion losses are less than 2.0dB and the isolation characteristics are higher than 30dB. The diplexer achieves a compact size (7.2 x 3.6 x 0.384mm³).

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This paper presents a compact multi-band/multi-mode power amplifier (PA) for mobile terminals. The PA is reconfigurable within the size of 6.2 x 8.05mm² and covers the frequency bands for mobile communications from 1.5GHz to 2.5GHz. The experimental results in terms of gain, output power, and adjacent channel leakage ratio are very close to those of actually-used single-band PAs in mobile terminals. To the best of our knowledge, this is the first time that a compact PA is presented that is less than 50mm² and covers the 1.5, 1.7, 1.8, 1.9, 2.3, and 2.5-GHz bands for GSM, W-CDMA, and LTE modes.

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New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupying low area, low power, low voltage and low phase noise. Also good stability can be obtained in this design. This structure also can be used for generating big multiples of reference frequency. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13um CMOS Technology.

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A new reversible data hiding algorithm for digital images is proposed in this paper. A single key parameter is derived in the algorithm during the hiding process. This parameter must be transferred to extract data. A 3 × 3 window slides over the cover image by one pixel unit, and one bit can be embedded at each position of the window. Thus, the ideal maximum hiding capacity is equal to the number of pixels in the image. As a result, significant increases in hiding capacity and better visual quality of message-hidden images may be achieved. The proposed algorithm is verified with simulations.

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Planning gaits for legged robots is an important and challenging task that requires optimizing parameters in a highly irregular and multidimensional space. Two evolutionary gait generation techniques using GA (Genetic Algorithm), GP (genetic programming) based on Cartesian and joint space are compared to develop fast locomotion for a quadruped robot. Optimizations for two proposed methods are executed and analyzed using a Webots simulation and real experiment of the quadruped robot. The performance and motion features of GA-, GP-based methods are compared and analyzed.

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Optimization of lithographic process plays a pivotal role in modern fabrication. Many parameters are engaged in optimizing optical systems used in lithographic process. In this paper, we show with a fixed rule for resolution enhancement techniques (RETs) we have an optimum value for image quality by definition of figure of merit (FOM). We find out how we are close to replicate a desired target mask on photoresist and derive an analytical formula for FOM versus numerical aperture (NA). The effect of variation in NA on quality of image that will be on photoresist is also shown.

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