A novel high accuracy fast speed operational transconductance amplifier (OTA) for switched-capacitor filters in 0.35µm CMOS technology is presented in this paper. The proposed OTA employs nonlinear current mirror and cross-pair structure to enhance the DC, AC and transient performance. Both simulation and experimental results are presented to show the performance boosting of the proposed OTA. Under the condition of 33µA quiescent current and a 30pF load capacitance, the experimental results of the DC gain, Gain Bandwidth, positive and negative slew rate have achieved as high as 62.5dB, 4.9MHz, 6.3V/µs and 8V/µs, respectively. Both GBW and SR are boosted more than one order compared to the conventional OTA.

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In this paper, we propose a level shifter circuit capable of handling a wide input voltage range. The circuit is based on a conventional two-stage comparator, and has a distinctive feature in that it operates a current amplification scheme for ultra low-power operation. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low power dissipation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low voltage input signals of 0.4V into 3V output signals. The power dissipation was 0.15µW at 0.4-V and 10-kHz input pulse.

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A novel circuit based on sign detection is introduced in this paper which uses the subtraction for comparing two numbers without carrying out a full comparison and conversion. Thus, the proposed schema decreases the delay significantly using only a little redundant hardware in contrast to previous works. Also the time complexity of the new design has the best results comparing to the previous work.

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In this paper, efficient reconfigurable finite-impulse response (FIR) filter architecture is presented based on a new coefficient representation method. The proposed binary signed subcoefficient method increases the common subexpressions and decrease the hardware usage and complexity. FPGA synthesis results of the designed two reconfigurable FIR filter architectures show that 33% and 27% reductions in the resources usage are achievable over the previously reported two state of the art reconfigurable architectures.

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This paper describes the design and realization of a multi-mode tracking feed antenna system, for a circularly polarized wave, which can generate sum and difference patterns suitable for monopulse tracking in remote sensing earth stations. It uses TE₁₁ and TE₂₁ modes, in a smooth circular waveguide, to obtain the sum and difference patterns. The higher order mode, TE₂₁ generated within the feed is separated from the fundamental mode, TE₁₁ by using a mode coupler. Circular polarization is converted to linear polarization by pin polarizer septum. The design of the multimode corrugated horn and polarizer are described in some details. The prototyped horn designed here operates in the frequency range of 7.2-8.8GHz. Sum and delta patterns and polarizer axial ratio are presented. The close agreement between measured and simulated data validates the present design.

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With the growing application of wireless networks, the forecasting technologies for wireless network traffic have played a significant role in network management, congestion control and network security. Local Support Vector Machine (LSVM) is an effective method to deal with model for wireless network traffic. To further improve the forecast accuracy and the real-time computing capability of LSVM-DTW-K algorithm we previously proposed based on LSVM, Hannan-Quinn information criterion (HQ) is used to calculate the number of the nearest neighbor points and Symbolic Aggregate Approximation (SAX) is used to symbolic the time series before using Dynamic Time Wrapping (DTW) algorithm to measure the similarity between two points.

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In order to meet the growing various customers' demands, several devices must be equipped in wireless personal area network (WPAN) environment. However, it causes a high cost and complexity to satisfy compatibleness within any WPAN devices. In this letter the multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband (UWB) system is considered with multiple access scheme, time/frequency domain spreading, and enlarged dual carrier modulation (E-DCM) for multirate transmission on only one electronic device in WPAN. It is shown that the proposed system can support multirate transmission based on the parameter.

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In this paper, a new compact but efficient Maximum Power Point Tracking (MPPT) circuit is added to the conventional battery charger. The battery charging is composed of two steps of the Constant Current (CC) charging and Constant Voltage (CV) charging. Unlike the conventional CC charging, the new MPPT circuit can adjust the charging current according to the sunlight intensity to deliver the largest available solar energy to the battery. For the CV, the proposed battery charger can keep its charging voltage on the full charge level thus it does not lose the battery capacity due to the undercharging. The new battery charger can deliver more power to the battery than the charger without MPPT by 98.8%. Also, the charging time can be shortened by 52.3% with 10.5% of layout overhead.

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This paper presents a low phase noise frequency synthesizer for WiMAX applications. The operating frequency of the proposed design ranges from 2.2GHz to 2.4GHz with a 1.25MHz spacing for the 1.25MHz to 40MHz channel bandwidth. The proposed VCO suppresses the phase noise effectively by adopting the Q-enhancement technique, the memory reduced tail current, and a noise filter. The high speed frequency divider is implemented by an improved TSPC D-flip-flop. The proposed design is fabricated in a TSMC 0.18µm CMOS 1P6M process. The measured phase noise is -118Bc/Hz at an offset of 1MHz from the center frequency. The fabricated chip consumes 25.5mW with a 1.5V supply and occupies a 1.1mm² die area.

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This paper proposes a method to analyze the behavior of the oscillating CNN (Cellular-Neural-Networks), and develops a way to design this system of Four-waves. After investigating the behaviors of the CNN cells, it provides a simplified model named One-cell model to calculate the frequency and the amplitude of the oscillating wave. And it finds a way to make CNN cells synchronized with fewer sub-harmonics. Then a method is presented to design the four-wave CNN array. Some corresponding simulation results are present to demonstrate the consistence between the results calculated mathematically and those simulated with SPICE. Simulation results on the designed 32×32 CNN array demonstrates that the designed system can synchronize well with four waves.

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High-performance algorithm and VLSI architecture for H.264/AVC context-adaptive, variable-length decoder (CAVLD) run_before computations are proposed to reduce the computation cycles. The run_before values of input symbols are estimated if they are zeroes in parallel. By skipping the estimation step when long symbols starting with ‘000’ are input, the architecture was drastically simplified while maintaining high performance. Experimental results showed that the performance for run_before computations improved by 68% on average when four symbols were estimated in parallel in comparison with sequential estimation of the symbols. The area of run_before is increased by 23% by the proposed architecture.

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This paper presents analytic expressions for T-type chain matching network synthesis of the power amplifier (PA) to enhance the performance at low output powers via a load impedance adjustment. Here, a parallel power amplifier for WCDMA B1 (1920-1980MHz) based on an InGaP/GaAs hetero-junction bipolar transistor (HBT) is utilized, which has a fully integrated matching network on a printed circuit board (PCB). As a result, the power amplifier shows a 38.7% power added efficiency (PAE), and a -37dBc adjacent channel leakage power ratio (ACLR) at 27.5dBm output during high power mode operation, and 17.6% PAE with a 22mA quiescent current and a -40.7dBc at a back-off output power of 17dBm during low power mode.

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This paper presents a buck converter with a switch-on-demand modulator (SOM) for achieving a fast transient response, small voltage ripple, and high power efficiency over a wide load range. Switching power MOS on or off depending on the energy demand of the load circuit results in a hybrid operation of pulse width modulation (PWM) and pulse frequency modulation (PFM). The proposed buck converter uses 90nm CMOS process and can achieve a transient response time of less than 2µs and a voltage ripple of 18mV at a load current range of 10mA∼500mA with a power efficiency above 88%.

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In this paper, performance enhancement techniques for CMOS power amplifier (PA) are proposed. First, a small inductor is inserted between the common-gate transistors of a triple-cascode stage (PA unit) for improving the power-added efficiency (PAE). Moreover, cross-coupled pairs are utilized in the PA circuit to raise the gain. Furthermore, these additional cross-coupled transistors can boost the PAE and saturated output power (Psat) of the PA. Based on these methods, a K-band PA has been designed in 0.18-µm RF CMOS process. Simulated results confirm these methods applied to this PA can effectively improve the performance in terms of gain, Psat, and PAE.

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The electro-acoustic radiation conductance is a quantitative parameter which characterizes the ability of transforming electric energy to acoustic energy on the ultrasonic transducer. To evaluate the performance of medical ultrasonic probe, we designed an electro-acoustic radiation conductance measurement system based on the radiation force balance method and the switching circuit unit for driving each element of array probe. The measurement results suggest that the developed system can be used reliably for the performance evaluation of medical ultrasonic array probes.

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