Using an analytical approach, new estimation of phase error in LC-Tank quadrature oscillators is proposed. The mismatches between passive components of LC tanks are considered as the reasons of the phase error. Closed form equations relating LC mismatches to phase errors are presented. To evaluate the analysis, a 5GHz quadrature LC-Tank oscillator is simulated using TSMC 0.18µm model technology. The results confirm the simplicity and high accuracy of the proposed analysis.

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Precorrelation bandlimiting, sampling, and quantization (BSQ) are three fundamental functions of receivers for global navigation satellite system (GNSS) signal processing. Analytical models have been developed to evaluate the implementation losses due to different combinations of these parameters for legacy modulations such as BPSK. However, the performance metric was losses of effective carrier-to-noise ratio in dB, instead of performance degradation of a delay-locked loop (DLL) used for code-tracking. This paper proposes an analytical model to predict the DLL performance with the loss of RMS tracking error in meters as the performance metrics. The signal model & assumptions and canonical form of DLL are first introduced. Then, analytical model is derived for DLL tracking accuracy and the performance metrics, tracking loss is defined. Finally, simulation results of two next-generation modulations for GPS and Galileo, namely CBOC and TMBOC, are presented.

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The current paper presents thermalcode addition technology as applied to an LDPC decoder to replace a variable node unit in the traditional adder. The proposed irregular quantization of thermalcode addition can generate information with regularity, which makes addition to the variable node executable by combinational logic circuit. With the original BER performance, code rate 1/2, and matrix (1296,648) in 802.11n standard, the simulation and logic synthesis results reveal that the presented LDPC decoder can save up to 21% of the hardware area.

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This paper proposes a compact multi-channel DTV signal generator. To combine multi-channel signal sources in digital domain, the baseband signal is up-sampled and interpolated using the modified Farrow-type filter. We formulate the optimization problem and design the filter coefficients. The designed filter contains a small number of multipliers with more than 40dB sideband signal suppression capability.

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The way-predicting (WP) cache is simple and energy-efficient when used as L1 cache. However, a concern in the WP cache is the speed of the slow hit. This paper proposes the use of way-lookup buffer (WLB) cache to alleviate the problem of slow hit in the WP cache. The results show that the WLB slow hit is 33% faster than the WP slow hit in L1 cache. This is important because the slow hit is often the critical path that determines the processor clock cycle time. The WLB cache is as energy-efficient as the WP cache when used as L1 cache; using the WLB cache can reduce the power consumed by the conventional L1 cache by 68%. Therefore, if we like the nice properties (i.e., simplicity and energy efficiency) of the WP cache but are reluctant to use it because the slow hit extends the processor clock cycle time, then the WLB cache is the one to use.

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Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.

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A time-interleaved sigma-delta modulator with VCO-based quantizer for next generation wireless applications is presented. This proposed modulator firstly introduces the VCO-based multibit quantizer into the time-interleaved sigma-delta modulator, which can achieve the improvement of the signal bandwidth and signal-to-noise ratio simultaneously. Moreover, these performance metrics have no adverse effects on power consumption, which is more suitable for wireless applications. A two-channel proposed modulator is taken as an example, and the simulation results show that the proposed modulator achieves a signal-to-noise ratio of 112.1dB over a 4.7MHz signal bandwidth with a clock frequency of 300MHz, which improves 100% in the range of signal bandwidth and 21dB in the signal-to-noise ratio compared to the conventional sigma-delta modulator with the same clock frequency and power consumption.

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The propagation threshold power through a white tight-buffered single-mode optical fiber was found to be 3% less than that through a transparent acrylate-coated fiber. This is because the white pigments in the buffer layer backscatter the visible emission that pumps a fiber fuse. Namely, the backscattered light is absorbed by the thermal decomposition product SiO in the glass melt surrounding the traveling plasma. This self-pumping effect was revealed by comparing the void trains left in fiber segments coated with white or black oil paint. This threshold reduction compels us to re-examine the power tolerance design of optical networks and fiber fuse terminators.

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We demonstrate that designing subthreshold digital circuits using only similarly-sized PMOS and similarly-sized NMOS transistors usually results in faster circuits than those scaled according to conventional design methods such as Logical Effort. This statement is valid if both transistor types exhibit the inverse narrow-width effect. For proving the claim, a number of circuits are designed in both ways, compared, and the results are reported.

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In this paper, we have derived a novel uniform asymptotic solution for the transmitted waves observed in the rarer medium when the cylindrical wave is incident on a plane dielectric interface from the denser medium. The validity of the novel uniform asymptotic solution has been confirmed by comparing with the reference solution calculated numerically. It is clarified that the transition wave plays an important role in the transition region. We have shown the interesting phenomenon that the lateral wave type transmitted wave is observed in the shallow and far region.

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In this paper, we proposed the branch metric recovery scheme to reduce the memory requirement of MAP decoding for double-binary convolutional turbo code. The proposed technique exploits the fact that huge memory size is required to store the branch metrics in double-binary convolutional turbo decoder. In the proposed method, rather than storing the original branch metrics, the partial terms of the branch metric are stored and the branch metrics are recovered with simple additions. The implementation results based on the proposed technique are presented to show the extremely low overhead compared to the huge memory reduction.

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We propose a simple design method for the Frequency Selective Surface (FSS) radome using an equivalent circuit model. Using a transmission and reflection method, the material properties, such as the permittivity and permeability of the FSS, were extracted from an FSS equivalent circuit model. Also, we propose a design equation for the resonant frequency of FSS radome due to the dielectric cover effect. The material properties of the FSS with dielectric covers were obtained and can be used to calculate the transmission characteristics of FSS radome. To validate the proposed method, the FSS radome is fabricated and the results of transmission characteristic are compared to the proposed method in this paper. The results were strongly positive. The method proposed herein can be used for the simple design and fabrication of an FSS radome and can be applied to the analysis of FSS radome for use with various communication systems and electrical instruments.

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The scalability achieved by partitioning of resources among clusters is still limited by traditional instruction encoding and centralized instruction execution control. This paper introduces a scalable unicore clustered architecture (SUCA). The instruction encoding encodes common information of sequences of instructions separately, thus reducing the amount of information in instruction words. The pipeline allows functional units to manage their own execution, thus releasing instruction issuing from instruction scheduling. SUCA can scale to 32 clusters with 1024 registers. Meanwhile, for the 4-cluster configuration, SUCA achieves an average of 13.3% speedup and a 4.6% improvement in frequency with reasonable hardware overhead, as compared with a traditional clustered processor.

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In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two signals without jitter accumulation issue. Moreover, it can be easily adapted for different FPGA families as well as implemented as an integrated circuit. The proposed serializer circuit is used as a part of a SERDES in inter-module communication in system-on-chip (SoC). The simulation and experimental results confirm the performance of the serializer with the proposed clock multiplier.

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