The paper presents a new mechanism for scan test scheduling in SOC (System On Chip) designs including isolated cores. Scan patterns instead of cores’ test pattern sets are treated as scheduling objects and the channels’ idle time during scan capture period can be utilized. Solution finding under this new mechanism is modelled as a bin packing under color constraint. Sequence pairs and simulated annealing algorithm are used to find the optimal scheduling solution. Experimental results obtained for several large industrial SOC designs show the feasibility of the proposed new mechanism.

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This paper presents a K-band CMOS low-noise amplifier (LNA) incorporating a Q-enhanced notch filter. The third-order notch filter composed of two capacitors and one high-Q inductor is used for low-side interference-rejection (IR). Moreover, the proposed inductor is realized by a tapped-inductor feedback topology to compensate its resistive losses with low-power consumption. The LNA is designed and implemented successfully in a standard 0.18-µm CMOS process. The circuit consumes 10.7mW with a chip size of 0.6mm². Measured results demonstrate 10.5-dB gain, 4.7-dB NF, 16-dB input return loss, 13.5-dB output return loss, -10.5-dBm input P_1dB, and -3.6-dBm IIP3 at 23GHz, respectively. The circuit also shows a 33.5-dB rejection level at 17.9GHz.

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In this research, a biomimetic acoustic sensor that can mimic the functional properties of basilar membrane in mammalian cochlea was fabricated with PMN-PT piezoelectric cantilever array. The piezoelectric cantilever array with ten different lengths was designed to obtain different resonant frequencies. It was fabricated by semiconductor processes and was poled to generate an electrical signal from an audible sound source. The fabricated acoustic sensor was tested by experimental setup. As an experimental result, the resonant frequencies of each cantilever and corresponding electrical signals were measured from 490Hz to 13,600Hz and the displacement sensitivity was measured with the audible frequency range.

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Electromagnetic wave properties in metamaterials including electromagnetic band gap (EBG) structures have been widely investigated due to their inherent capabilities for developing novel devices in the fields of optics, microwave and antenna engineering. In reality, most of the materials are dispersive or frequency-dependent, on the other hand, it is important to investigate how the performance of EBG structures depends on frequency. We propose herein a new finite-difference frequency-domain (FDFD) algorithm for band structure analysis of two-dimensional EBG materials composed of Drude-type dispersive media. This method is shown to lead to highly accurate and stable band structure calculation.

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In this paper, a multiple valued register file (MVRF) with 2-read 1-write circuit is designed in TSMC Low Power 65nm CMOS. High V_TH and Low V_TH transistors are organized together to realize a multiple-threshold Literal Gate, and then connect with pass-gates to implement ternary valued register file cell. The information density of the proposed MVRF cell achieves a 61% improvement compared to a standard 6T SRAM, and more than 140% improvement compared to a binary register file. In addition, the quantity of the word line and bit line reduces about 33% compare to a standard 6T SRAM, which also improves the system information density. An 8×8 MVRF array have been designed and simulated in terms of power, speed and cell stability. Simulation results show that the MVRF array operates at 1.0GHz, consuming 1.2mW at 1.2V.

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A novel ultra-wideband (UWB) monopole antenna with triple band-notched functions is presented. A pair of folded multiple-mode resonators (MMR) symmetrically coupled to the feed line are utilized to generate triple notched bands for WiMAX, WLAN and downlinks of X-band satellite communication, respectively. The centre frequencies and band gaps between them can be tuned by varying the length and width of the MMR. Simulated and measured results of the proposed antenna have been displayed and good agreement between them has been achieved.

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This paper presents a module that solves the square root by obtaining a number of more significant bits from a look-up table as an approximate root. A set of possible roots are then appended and squared for comparison to the original radicand, finely tuning the calculation. The module stops as soon as it finds an exact root, therefore not all entries take the same number of cycles, reducing the number of iterations required for full resolution. The proposed FPGA module overcomes a Xilinx’s logiCORE IP in terms of resources utilization and in several cases latency due to its flexible structure configuration.

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The combination of multi-core, SIMD and VLIW schemes is becoming prevailing in today’s media processor architectures. To achieve a deep insight into this trend, we propose a power conscious performance model based on the rationale of Hill and Marty’s model. Several representative media application kernels are evaluated on the proposed model. The evaluation result shows that: for none communication applications, a large number of small cores achieve optimal performance; for communication applications, architectures with reduced core count and increased core size is preferred. Meanwhile, by increasing the SIMD width, better power efficiency can be achieved for both types of applications at a small loss of performance.

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This paper proposes an algorithm that maps target patterns onto parallel string matching architectures in intrusion detection systems (IDS). In the proposed iterative pattern mapping, the sets of patterns that are mapped onto string matchers are sorted in ascending order of the average pattern length in each turn. By mapping a set of patterns for a string matcher onto the other string matchers repeatedly, the required number of string matchers is reduced. Therefore, the proposed iterative pattern mapping minimizes the total memory requirement for parallel string matching architecture.

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This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low voltage headroom operation at 0.5V. This mixer is simulated and verified in 0.13µm standard CMOS technology. The result shows a conversion gain (CG) of 11.84dB, 1dB compression point (P_1dB) at -14.36dBm, third-order intercept point (IIP3) of -5dBm and a noise figure (NF) of 15dB and with a power consumption of 930µW.

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A novel silica waveguide lens is proposed for use in free-space optical cross connects. It comprises a core-cladding stripe structure that acts as a phase modulator in the lens region. Beam propagation method (BPM) simulation results show that the phase is greatly similar to the approximated profile calculated by ray tracing. However, higher modes due to the rough lens profile leads to energy loss of below 0.8dB. Further losses are expected from scattering due to the elimination of vertical beam confinement. The collimator also shows low wavelength and polarization dependence.

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In this paper, a new in-package high efficiency voltage down converter (VDC) is presented. Usually, quality factor of inductors is the main problem for generating high efficiency DC-DC Converters. In order to mitigate this problem, Bonding Wires with a new form are exploited in which four mutual inductions of bonding wire are used to increase the total inductance. This technique provides a high quality and low space in-package inductor with negligible parasitic elements. The peak efficiency for the proposed circuit at 50MHz switching frequency is around 86% with 150mA loading current.

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