In the traditional digital channelized receiver, there is no simple algorithm to reconstruct the wideband cross-channel signal without distortion. Moreover, the analog-to-digital converter (ADC) limits the instantaneous bandwidth and dynamic range of the receiver. These problems restrict the applications of digital channelized receiver in radar and communication. Based on the principle of signal matched-phase, a novel channelized receiver structure is presented, where the sub-channels can be seamlessly combined. The presented structure uses the principle of signal matched-phase to solve the frequency ambiguity in the case of the multi-channel undersampling signals. It can reconstruct the wideband cross-channel signal with extremely low distortion, and that it avoids the use of high-speed and high-resolution ADC in wideband and high dynamic applications. Simulation results show the effectiveness of the structure.

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We propose a measurement method of photodetector frequency response. This technique is based on a heterodyne principle, where a high-extinction ratio Mach-Zehnder modulator is used to generate a two-tone lightwave as a stimulus signal up to millimeter-wave frequency bands. Our proposing method can provide a relatively short traceability chain to optical and electric power standards.

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This paper presents a novel methodology for IC speed-up in 32nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, we develop the boosting structures that can improve the signal propagation on interconnect significantly. Furthermore, the circuit area and power dissipation issues are also taken into account. With the addition of boosting path, the full booster can reduce the delay of interconnect as much as 50% while consuming merely more than 18% of power. In the high-speed and low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between the power consumption and high performance which play an important role in application-specific integration circuits in the 22nm node and beyond.

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Seamless mobility support in a heterogeneous roaming environment is one of several challenging issues for next-generation wireless network, and handoff decision is an important and intelligent part of seamless handoff process. In this paper, an improved game theory-based vertical handoff decision algorithm is presented. The proposed algorithm formulates the relationship between mobile nodes and heterogeneous access networks as a special consumer goods market model, and formulates the relationship among candidate access networks as cooperative game process. The simulation experimental results show that the proposed network selection algorithm is able to achieve the load balancing well, and make the networks obtain larger payoff.

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The current paper presents an improved bandgap voltage reference (BGR) that utilizes curvature-corrected current generators which compensate for the voltage reference at lower and higher temperature range. The voltage reference is operated with a supply voltage of 2.5V to achieve an output reference of 1.1835V. The temperature coefficient achieved from the circuit is 1.342ppm/°C, resulting from temperature changes between -50°C to 125°C, sixfold improvement from first-order BGR. The proposed circuit is simulated using Silterra 0.13µm CMOS technology.

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We fabricated a diode-pumped mode-locked Ti-diffused Er-doped LiNbO₃ (Ti:Er:LN) laser with a SiO₂/TiO₂ dielectric multi-layered mirror. The lasing threshold power was 70mW at 1484nm, and the slope efficiency was 1.48%. Stable optical pulses with a width of 10.86ps were measured by driving the phase modulator at 13.575GHz.

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An aperture-coupled multi-layer broadband microstrip array antenna with coupling ring slots and modified ring patches is presented. The structure of the array consists of a 3-dB 180°-phase shifter, two 1-port's and two 2-port's aperture-coupled microstrip antennas. All parts of the array antenna are designed for broadband operation. The array antenna works based on the back coupling to the microstrip line of 2-port aperture-coupled antenna. Simulation results of the array display encouraging properties, such as wide impedance bandwidth of 77% for |S₁₁| < -10dB and nearly stable gain. The maximum gain of the array antenna is almost 12.65dBi at 5GHz. The radiation efficiency, radiation pattern, side-lobe level and cross-polarization are also adequate within the impedance bandwidth between of 3.34 and 7.53GHz.

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A novel spiral antenna that simultaneously radiates circularly and linearly polarized waves is presented. The antenna achieved radiating omnidirectional circularly polarized waves by shaping a spiral antenna as its looks like a cross. Moreover, putting a parasitic element close to it, it succeeded in being utilized as a linear polarization antenna at the same time. This paper explains the reason why the antenna radiates multi-polarization waves and how the antenna is designed in order to utilizing frequencies. Experimental results of return losses, radiation patterns and axial ratios of a prototype antenna are shown for verifying its performance. The antenna can be expected to be used for multifunctional mobile communication devices, because it is a single feed and single layer printable antenna.

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We propose a fractional-N PLL synthesizer with 15µsec start-up time featuring an open-loop VCO capacitor coarse setting and subsequent VCO control voltage setting technique with a nonvolatile memory, which can eliminate the frequency detection and VCO coarse tuning sequence used in conventional start-up acceleration techniques. The on-chip nonvolatile memory fabricated in a standard CMOS technology stores the predetermined calibration data to overcome the process variations in VCO capacitors and varactors. A prototype PLL is designed in a standard 0.18µm CMOS technology with die size of 950µm x 515µm and 10.4% area overhead of the acceleration circuits, and presents the measured start-up time of 14.6µsec.

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This paper proposes an RF signal generator using a time domain harmonic suppression technique based on Fourier series analysis. The circuit consists of four differential ring voltage control oscillators (VCO's) with phase differences and the pulse signal summing circuit. By summing pulse signals from VCO's with appropriate phase differences determined by Fourier series in time domain, the third and fifth harmonics can be cancelled without filters. To confirm the validity, a prototypal RF signal generator was fabricated in 90-nm CMOS technology. As a result, we succeeded in generating an RF signal from digital pulse signals. The frequency range is from 1.1 to 3.7GHz with 1-V power supply. The suppression of both the third and fifth harmonics are below -48dBc at 1.1GHz and -42dBc at 3.7GHz.

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In this paper, a novel thin card-sized on-metal 953MHz UHF RFID tag is presented. The RFID tag operates in a unique configuration with an IC chip mounted on a small metallic loop and a radiative mushroom structure. A card-sized 54×86×0.94mm³ tag is designed successfully with a reasonable IC impedance matching with appropriate loop dimensions. It is shown that the reading range performance is tolerant of the environment and the measured reading range is 2.6m on a large 200×300×2mm³ metal board. The reading range is 0.1m longer than a commercial card-sized on-metal tag with much larger thickness of 1.8mm.

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Mapping matrix operations on SIMD processors brings a large amount of data rearrangement that decrease the system performance. This paper proposes a Configurable Matrix Register File (CMRF) that supports both row-wise and column-wise accesses. The CMRF can be dynamically configured into different operating modes in which one or several sub-matrices can be accessed in parallel. Experimental results show that, compared with the traditional Vector Register File (VRF) and the MRF, the CMRF can respectively achieve about 2.21x and 1.6x average performance improvement. Compared with TMS320C64x+, our SIMD processor can achieve about 5.65x to 7.71x performance improvement by employing the CMRF.

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An efficient recovery method for thread-level speculation (TLS) is proposed. The method tracks the inter-thread data dependence as a method for identifying those threads that are obviously unaffected by a data dependence violation. The method is simple to implement. Still, the simulation results using benchmark applications show that the method can significantly reduce the number of unnecessary thread restarts and consequently improve the performance of TLS. Specifically, when compared with the baseline TLS, TLS with the proposed method is 2.3 times faster for IS, 1.7 times faster for equake, and 3.5 times faster for mcf with the use of 64 cores. With the method, the performance of TLS increases steadily up to 64 cores for IS, equake, and mcf, while the speedup of the baseline TLS starts to saturate at 8 or 16 cores.

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This paper proposes a novel tag collection algorithm for improving the performance of iterative tag collections in active RFID systems. In the proposed tag collection algorithm, a reader assigns fixed response slot numbers to the tags newly identified via a tag numbering phase, and then collects additional data sequentially from all the tags without tag collisions in the following tag collection phase, in which the tag responds in its own assigned slot. This lowers the cost of empty slots and collided slots during iterative tag collections. The simulation results showed that the proposed tag collection algorithm could achieve higher tag collection performances as the tag mobility was lower, compared with the standard tag collection algorithm and the modified tag collection algorithm that was proposed in a previous study.

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This letter presents the experimental investigation to increase the sensitivity of an optical fiber refractive index sensor with a multimode interference (MMI) structure. It is confirmed that the interference wavelength can be set in the long-wavelength region by adjusting the sensing-part length. Moreover, it is shown that the fineness of the cores in the input and output fibers is essential to obtain a sharp interference signal. We demonstrate the high sensitivity of an MMI-structured optical fiber sensor by applying it to refractive index measurements of ethanol/water solutions. This refractive index sensor reveals a resolution as fine as 1.8 × 10^-5, which is the highest value so far reported in this type and has one order higher sensitivity than a commercially available Abbe refractometer (∼ 10^-4).

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We explore a dual-band fractional-N PLL synthesizer with 3.5mW, 5µsec settling time and 15µsec start-up time in 0.18µm CMOS technology. The power consumption is minimized through the design efforts in LC-VCO design to maximize the quality factor of an integrated inductor up to 6.1 at 866MHz and minimize the VCO gain by a capacitor tuning technique with an on-chip nonvolatile memory and the proper choice of varactor. Measured results of a prototype fractional-N PLL satisfy the required settling and start-up times, and indicate that the phase noises at 10kHz and 100KHz offset are -108.7dBc/Hz and -98.3dBc/Hz, respectively, and the reference spurious level is -81.6dBc.

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Sequential Compressive Sensing, which may be widely used in sensing devices, is a popular topic of recent research. This paper proposes an online recovery algorithm for sparse approximation of sequential compressive sensing. Several techniques including warm start, fast iteration, and variable step size are adopted in the proposed algorithm to improve its online performance. Finally, numerical simulations demonstrate its better performance than the relative art.

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The goal of this research is to design a PRAM-based SSD (solid state disk) updating management scheme which uses PRAM for main logging area of previous hybrid SSDs. Specifically the proposed scheme can provide higher performance and longer lifetime than those of previous scheme. Simulation results show that overall write performance can be enhanced by around 380% on average and the lifetime of SSD can be increased by up to 6.5 times.

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