The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present an efficient unsigned parallel squarer design technique. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 18% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, area, propagation delay and power consumption can be further reduced up to 26%, 15% and 25%, respectively.

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In this paper, a power amplifier system with a bi-purpose auxiliary amplifier is suggested to provide improved efficiency and linearity. This auxiliary amplifier acts as an IMD3 canceller, as well as an efficiency enhancer of the power amplifier. From the design equations of power amplifier systems with main and auxiliary amplifiers, the conditions required to cancel out the IMD3 and to expand the input range to achieve high efficiency are suggested. The IMD3 cancelling is adjusted by controlling a transition parameter of the auxiliary amplifier, and the efficiency enhancement is achieved by the early saturation of the main amplifier at a lower input power, while the auxiliary amplifier supplies the additional power. For the purpose of verification, a power amplifier of 25dBm at 2.35GHz was simulated and implemented with two class-F power amplifiers. The measurement results show a maximum IMD3 improvement of 24dB and peak efficiency of 75%. This work is expected to be useful for the design of efficient power amplifiers with reasonable linearity.

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In soft-decision fusion- (SDF-) based cooperative spectrum sensing, weighting the coefficients vector is the main factor affecting the detection performance of cognitive radio networks. In this paper, the use of particle swarm optimization (PSO) algorithm as a prominent technique is proposed to optimize the weighting coefficients vector. The proposed PSO-based scheme opts for the best weighting coefficients vector, leading to improved detection performance of the system. The performance of the proposed method is analyzed and compared with genetic algorithm- (GA-) based technique as well as other conventional SDF schemes through computer simulations. Simulation results validate the robustness of the proposed method over all other SDF techniques.

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The real time anticipation of robotic task is important in finding and correcting the error in CPU of robot, which may designed using by bit parallel-iterative CORDIC circuit. This paper proposed pass transistor logic based multiplexer, register, full adder and basic logic gates that are implemented into bit parallel-iterative CORDIC basic circuits. The circuits are designed using by DSCH2 CAD tool and layout are generated by microwind 3 CAD tool. The parameter analysis done by BSIM4 analyzer. The CPL CORDIC circuit is compared with conventional and CMOS CORDIC circuits that give better performance in terms of speed, power consumption and area. The analyses are extended to Fast Fourier Transformation (FFT).

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In this paper, we analyze the interstation direct wave interference (IDWI) under an asynchronous condition. We propose an array calibration method for the consistency of gain-phase for the first time and show the conditions and probability of the generation of IDWI and the characteristics of asynchronous IDWI. This method can implement calibration of direct wave without keeping radar stations in synchronous condition and perform outstanding precision and stability. The experimental data demonstrate that using array calibration for gain-phase errors based on asynchronous IDWI can get accurate and stable calibration values of gain-phase errors.

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Differential Power Analysis (DPA) aims at revealing secret keys in cryptographic devices by analyzing their power consumption as side-channel information. Although power consumption models based on transition probability were used to evaluate a DPA-resistance in previous studies, the adequacy of this model has not been confirmed enough. In this paper, we show two experiments about information of power consumption precisely, and show that Random Switching Logic which is one of the DPA-countermeasures is in reality not secure against DPA.

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A simple iterative receiver for general nonorthogonal unitary space-time constellations (NOUSTC) is proposed. The output of the conventional noncoherent detector is used to initialize the receiver. In each iteration, the decision from last iteration is used to transform the received signals to derive new signals that bear channel state information (CSI), which are then employed to estimate the CSI using a Wiener filter, following a coherent detector is implemented. In our scheme, for each time block we can use not only the past and the present CSI-bearing signals, but also the future ones, to estimate the CSI, thus resulting in a relatively refined channel estimate and ultimately a receiver with good performance. Simulation results verify the performance of the proposed receiver.

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This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

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We propose a 32-bit 16-program-cycle nonvolatile memory fabricated in a standard 0.18µm CMOS technology based on a channel hot-electron trapping at the transistor gate sidewall. Its target application is calibration of RF/analog circuits for multiband/multimode communication systems, that demands in-field multiple-time programmability and data select-ability. The issue of the one-time programmability in the proposed memory cell is overcome by the addressing memory cell array, and the promised reliability is observed through the optimization of program and restore operations. The developed nonvolatile memory is applied to a dual-band PLL synthesizer with an area overhead of 8.5%.

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One of the topologies that can work at high Power and high Quality simultaneously is the DCI-NPC topology. This new topology has new parts and presents new voltage and distortion errors. One of these new elements are the MOSFET parasitic Diodes. These Parasitic-Diodes presents a Recovery Reverse Time (t_rr) and its distorting effects generates signal and quality losses, and EMI problems. These phenomena are introduced, modeled, studied and evaluated to discuss the affectation importance of the Recovery Reverse Time value in the Multilevel Power Amplifiers performance.

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A low-voltage differential version of a high performance voltage follower is presented. The proposed circuit is very compact, and symmetric with respect to the input devices. Both differential input devices are enhanced by local shunt feedback, increasing the gain and, thus, reducing the output resistance for higher precision. The circuit has proved useful as a winner-take-all (WTA) circuit. It also features operation as a fully differential amplifier with low supply voltage requirements close to a transistor's threshold voltage. Experimental results verifying the operation of the proposed structure are provided.

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If a duty ratio and a load resistance in a boost DC-DC converter are changed, the characteristics is varied greatly, that is, the boost DC-DC converter has the non-linear characteristics. In many applications of DC-DC converters, loads cannot be specified in advance, and they will be changed suddenly from no load to full load. The boost DC-DC converter used a conventional controller cannot suppress output voltage variation caused by large load change. In this paper an approximate 2-Degree-of-Freedom (2DOF) digital controller for suppressing the output voltage variation at sudden load change is proposed. This controller is actually implemented on a micro-processor and is connected to the boost DC-DC converter. Experimental results demonstrate that this type of digital controller is effective to suppress the variation.

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Low-power dual-supply clock networks based on novel level-converting clock gating cells are presented. The proposed clock networks achieve a substantial power saving with mitigated timing constraints on gated clocks. They also allow pulse-based flip-flops used at leaf clock nodes to work with no pulse generators, resulting in more power saving and area reduction. The proposed dual-supply clock networks were designed in a 32nm CMOS technology. The evaluation results indicated that the proposed clock-gating cells have up to 24.8% smaller power with 74.3% reduced latency and 17.5% reduced area. They also indicate that the power consumption of the proposed clock networks was reduced by up to 30.3%.

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The evolution of Android smartphone has increased the importance of touchscreen capabilities as user interaction as well as user input method. However, due to the limitation of Android architecture, every touch event may not create its corresponding display update all the times. To overcome this limitation, this paper proposes a novel technique of Touch Event Handling Block (TEHB) with capability of virtual touch event generation and low pass filters. TEHB is implemented on Android 2.2 and its performance simulations show that TEHB can achieve more performance gain than conventional triggering method.

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A novel Digital-to-Analog Converter (DAC) utilizing Tribonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The proposed DAC has the features that the DNL can be superior to that of a binary DAC and the INL can be superior to that of a unary DAC. In the proposed DAC on a 0.18µm CMOS process, the number of logic gates can be achieved an around 52% reduction compared to that of the unary DAC.

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In general terms, it is not possible to establish symbolic explicit analytic expressions of the operating point and transient analysis for circuits containing diodes modelled using an exponential function. Therefore, this work propose replacing the diode for an equivalent circuit obtained by using a power series and a Taylor series consecutively. Finally, we present a symbolic solution for some circuits that include diodes; resulting for the best case: for DC analysis a relative error of 1E-11 and for transient analysis a relative error ≤ 5E-4.

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The electromagnetic shielding and polarization characteristics of carbon fiber reinforce plastics (CFRP) based on unidirectional (UD) materials are determined by experiments. The UD CFRP laminates have single direction carbon fibers, which behave the same as wire-grid structures. The measured transmission coefficient for the 1 ply UD CFRP laminate is about -2dB, when the direction of the carbon fiber is perpendicular to the incident wave. The polarization ratio is more than 20dB for most frequency points. In addition, it is confirmed that the transmission coefficient can be controlled by rotating the UD CFRP laminates.

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Orthogonal Frequency Division Multiplexing (OFDM) system became an important material for the current researchers. As like other communication systems, OFDM system needs to employ the channel coding to reduce the Bit Error Rate (BER) such as the concatenated Reed Solomon-Convolution code (RS-CC). To enhance more the BER problem, a Reed Solomon-Recursive Convolution code (RS-RCC) over Additive white Gaussian noise (AWGN) and fading channel has been used in this letter with same complexity of (RS-CC). The simulation results prove that the suggested method for different kinds of constellation mapping of various coding rates gives better BER performance than the old method represented by RS-CC.

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We propose the lateral integration scheme of an MEMS tunable VCSEL and a slow light amplifier for increasing single-mode power. The modeling result predicts the maximum output power over several tens mW for a compact slow light amplifier monolithically integrated with an MEMS VCSEL. In addition, the efficient excitation of slow light in the integrated slow light amplifier is shown. A high coupling efficiency and a radiation angle from the amplifier are almost constant during wide wavelength tuning.

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The extended Internet group management protocol (EIGMP) is a method which allows simultaneous reception of channel streams being broadcasted for other users in shared networks. Recently, implementation of EIGMP in gigabit Ethernet passive optical network (GEPON) was suggested to reduce the channel change response time (CCRT) especially for Internet protocol television (IPTV) systems. In this paper, we extend EIGMP in gigabit-capable PON (GPON) with a cross-layer approach. With the proposed method, the CCRT in GPON can be reduced by up to 10.3% in comparison with that of traditional IPTV systems.

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This paper proposes self-selection pseudo-circuit (SP), a simple and effective approach to increase switch connection reusing rate and improve the network performance. It especially suits the network in which the performance is dominated by the number of hops. In SP scheme, multiple switch connections are allowed to be reserved for one inport, and the flit can reuse the partial switch connection(s) based on the routing information. For the evaluation with the traces from Splash-2, SP reduces the interconnection latency by up to 21.6% (16.9% average) with 16-core CMP configuration, and 22.2% (19.5 on average) with 64-core CMP configuration. Evaluated with synthetic traffic, the proposed scheme decreases the latency up to 19% (16% average).

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A process, voltage, temperature (PVT) insensitive boosted charge transfer (BCT) circuit for charge-domain (CD) pipelined analog-to-digital converters (ADC) is presented. The output charge of existing BCT varies extensively with PVT variation, leading to large common-mode charge errors in each differential BCT stage when used in CD pipelined ADCs. Therefore, complicate common-mode control circuits must be adopted to stabilize the common-mode charge of each stage, which consumes large power and chip area. The proposed BCT circuit employs a differential difference amplifier and a differential voltage reference to reject the charge errors caused by PVT variations. A 125-MSPS, 10-bit CD pipelined ADC without common-mode control circuit is implemented based on the proposed BCT, consuming only 27mW from a 1.8V supply.

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A novel RC time constant tuning technique for continuous-time delta-sigma modulators is proposed to alleviate the systematic time constant shift originating from process variations. The proposed tuning technique uses programmable current sources instead of capacitor banks in order to reduce the implemented die area. MATLAB/Simulink simulation results demonstrate that this technique can achieve the desired SQNR even with ±30% RC time constant shifts.

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An adaptive digital predistortion (PD) technique is proposed for linearization of power amplifiers (PAs) in multiple-input multiple-output (MIMO) transmitters. We consider a PD structure equipped with only one combined feedback path while conventional systems have multiple feedback paths. Hence, the proposed structure is much simpler than that of multiple feedback paths. Based on the structure, a new PD algorithm is derived. The simulation results show that linearization performance of the proposed method is almost the same as the conventional multiple feedback technique while the former is much simpler to implement than the latter.

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We propose an interference alignment scheme for the multi cell multiuser interference channel, where M antennas are used at the base stations and N antennas are used at user terminals. The large number of interference vectors from other cells are aligned into interference alignment planes at the other cell base stations. After the alignment, L cells support up to L(⌊N/(L-1)⌋-1) user streams when 1≤⌊N/(L-1)⌋≤M.

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This paper presents a broadband single-pole double-throw (SPDT) transmit/receive (T/R) switch implemented in a standard 0.18-µm CMOS technology. The switch uses a grounded inductor, transistors in deep n-type wells, resistive body-floating components, a negative control voltage, and lowpass networks to improve its insertion losses, power-handling capabilities, and isolation. Moreover, the switch featuring a bandpass response results from the grounded inductor and the lowpass networks. To select T/R modes, the control voltage is under ±1.8-V operation. The insertion loss, input return loss, return loss, and isolation of the switch are 2.7±0.4dB, >14.3dB, >10.2dB, and>32.8dB from 6GHz to 32GHz, respectively. The input P_1dB is 22.6±1.6dBm at the frequencies of interest.

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A variable power divider to be 3:1 and 1:3 power division ratios with the good inputmatching characteristic is proposed and fabricated. The proposed power divider has an ungrounded copper plane under two power-dividing lines. The power-dividing line becomes a microstrip line or a coplanar line based on the operating conditions of the ungrounded copper plane. The fabricated power divider at a center frequency of 1.5GHz stably provides power division ratios of 3.2:1 and 1:3.2, with S₁₁<-20dB over the frequency range 0.97-2.22GHz.

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This paper introduces a Bilinear Skewed Parallel Memory (BilisPM), which can support multiple conflict-free access types and the circular addressing in X-Y directions of the 2D space. BilisPM features matched Memory Modules (MMs) and can effectively save the on-chip area. We introduce the formal specifications of BilisPM and give its hardware implementation. Experimental results show that BilisPM can reduce the chip area by 22.7% on average (38.1% at most), and its controller consumes smaller chip area at reasonable critical path delay, as compared with the traditional schemes with unmatched MMs.

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