This paper presents a pipelined analog-to-digital converters (ADCs) calibration method that integrates ant colony optimization (ACO) algorithm with time-delay neural network (TDNN). The proposed method uses TDNNs to calibrate the integral nonlinearity error of the ADC, and leverages the global search capability of ACO to optimize the time-delay feature dimensions and the initial parameter configuration of the neural network. This approach improves the calibration performance, reduces the model size, and avoids converging to local optima. The calibration method was evaluated using a commercial 14-bit, 1Gsps pipelined ADC chip. The results show that this method improves the SNDR from 63.80 dB to 79.31 dB, SFDR from 82.50 dB to 95.65 dB, and ENOB from 10.31 bits to 12.88 bits. Additionally, this method identifies the optimal time-delay feature combination with a 100% probability of global optimal calibration performance.

In this letter, a low-profile substrate-integrated magnetoelectric dipole antenna was designed. Three layers of Rogers 5880 substrates stacked in the longitudinal direction. Electric dipole and magnetic dipole were realized by top rectangular patches and middle meandering structure, respectively. Through a surface current plot, it was found that the electric dipole worked by the electromagnetic coupling from the magnetic dipole, and hence the working mechanism was figured out and a low profile was achieved. By fabrication and measurement, the proposed antenna has a bandwidth from 3.08 GHz to 4.07 GHz (27.7%) for |S₁₁|<−10 dB. Boresight gain is 9.045±0.905 dBi. The profile is only 0.06λ₀ (λ₀ is the center wavelength). Measurement and simulation agree well with each other. Therefore, the proposed design can be used on the planar communication equipment with low-profile demands.

The vibration energy harvesting properties of Fe-based nanocrystalline soft magnetostrictive material (Fe-Si-B-P-Cu-C) thin films were systematically investigated. Thin films were deposited using rotational sputtering and subsequently annealed. Nanocrystallization occurred in the samples annealed at 100-110% of the crystallization temperature. This nanocrystallization process enhanced soft magnetic properties, however, decrease saturation magnetostriction reflecting the influence of the negative magnetostrictive α-Fe phase. The film annealed at 105% of the crystallization temperature exhibited the highest vibration power generation performance. This superior performance was attributed to the combination of enhanced soft magnetic properties, high saturation magnetic flux density, and a relatively large saturation magnetostriction.

To solve the problem pertaining to voltage overshoot arising from frequent switching in CAN transceiver interface circuits, and to mitigate electromagnetic interference while protecting the circuit, this paper proposes a new low-voltage overshooting CAN transceiver interface circuit based on a 0.18μm BCD. The high-voltage switching transistor is controlled by comparing the bus voltage with a reference voltage to achieve real-time monitoring and protection of the bus voltage. The simulation results show that the interface circuit has excellent power consumption, anti-interference ability, and signal integrity, with a power consumption of 24.2μA and bus voltage symmetry of 0.934-1.052 under the passive state of the bus.

A push-pull buffer with source degeneration output structure is proposed as an intermediate stage for an output capacitorless low-dropout regulator (OCL-LDO) in this paper. The proposed push-pull buffer with source degeneration output structure can increase the current for charging and discharging the gate capacitance of the power transistor during the transient instant, effectively improving the transient voltage slew rate at the gate of the power transistor, thereby enhancing the transient response of LDO. Additionally, a transient overshoot reduction (TOR) circuit is employed to suppress the overshoot phenomenon during transient response. The proposed LDO is implemented using 0.18 µm CMOS technology. Simulation results indicate that the LDO can operate from a supply voltage of 1.2 - 1.8 V with a minimum dropout voltage of 0.2 V at a maximum 50 mA load and quiescent current of 22 µA. With a load current step from 200 µA to 50 mA within 10 ns, the maximum value of the voltage spike is 160 mV and the maximum recovery time of the LDO is 0.88 µs.

This paper presents an output capacitor-less LDO regulator (OCL-LDO) with high PSR and ultra-low quiescent current. The circuit utilizes a local feedback amplifier based BGR and a pseudo-dynamic biased error amplifier to improve its PSR. Hereinto, the modified super source follower solves the stability problem in the local loop and further reduces the output impedance. Furthermore, the nested miller compensation based on dynamic nulling resistor (DNR-NMC) is utilized to keep stable in the full load range. The transient enhancement circuit can reduce the overshoot and outshoot voltage by 68% and 35%, respectively. This design implemented in 180nm technology occupies an area of 0.132μm² and provides a controllable output over a supply range of 2.5V-5V and the maximum output current is 100mA. The PSR is less than -75dB at 100Hz and -40dB at 10kHz with the load current of 100mA. Additionally, the line regulation and load regulation are 0.08%/V and 0.21%/A, respectively.

The switching characteristics of four 650V power devices were compared: (1) Cascode GaN-FET, (2) SiC-MOSFET, (3) Si-SJ-MOSFET, and (4) Si-RC-IGBT. Using double pulse tests, the characteristics of two configurations ((a) Schottky Barrier Diode/Transistor (Tr), (b) Tr/Tr) were evaluated. In both configurations, the Cascode GaN-FET had the smallest switching loss, less than half that of the other devices. The SiC-MOSFET had a smaller transconductance than the other devices, and the turn-on loss in configuration (a) was slightly larger than those of the Si devices. In configuration (b), the turn-on losses of the two Si devices were significantly larger than those in (a) due to the recovery current of the internal diodes of the transistors.

A 28GHz noise-cancelling low noise amplifier (LNA) in standard 65nm CMOS technology is introduced for millimeter-wave application in this letter. The proposed LNA implements transformer-based noise-cancelling technique to cancel the in-phase noise from main and auxiliary amplifier while strengthening the combined signal. A gain-boosting transformer is employed to improve gain with minimized power consumption. Current-reuse technique is further introduced to reduce power consumption overhead. This work achieves a gain of 27dB and a minimum noise figure (NF) of 2.5dB with only 4.4-mW LNA stage power consumption.

In this paper, a contact pressure online monitoring method of PP-IGBT based on the ultrasonic measurement is proposed. A finite element (FE) model of PP-IGBT is established. The dynamic contact pressure within PP-IGBT during power cycling process is analyzed based on the FE model. An ultrasonic measuring system for contact pressure measurement of PP-IGBT considering the structure of the device and fixture is designed. A temperature compensation method using coupling interface reflection wave is proposed to eliminate the influence of temperature on measuring the contact pressure. A power cycling test platform is established to verify the effectiveness of the proposed method. Results show that the proposed method can realize the non-invasive online measurement of the contact pressure in PP-IGBT.

In this study, we developed a high-frequency electric field imaging system based on the first-order electro-optic effect for the detection of time-varying frequency wave sources. The proposed system utilizes the optical heterodyne technique. The process begins with an antenna that detects the frequency of the electric field of interest, which is then fed into the optical local oscillator (LO) signal generation system. This optical LO signal tracks the frequency of the electric field being observed while maintaining a constant intermediate frequency. This configuration enables the visualization of dynamic electric fields, including asynchronous wave sources and frequency-modulated signals, without requiring a direct physical connection to the wave source. In this study, we present the development of a high-frequency electric field imaging system based on the first-order electro-optic effect for the detection of time-varying frequency wave sources. The proposed system utilizes the optical heterodyne technique. The process begins with an antenna that detects the frequency of the electric field of interest, which is then fed into the optical local oscillator (LO) signal generation system. This optical LO signal is designed to follow the frequency of the electric field being observed while maintaining a constant intermediate frequency. This configuration facilitates accurate electric field imaging and enables the visualization of dynamic electric fields, including asynchronous wave sources and frequency-modulated signals, without requiring a direct physical connection to the wave source.

In this paper, a novel on-chip digital soft-start circuit is proposed to realize the suppression of inrush current and overshoot voltage in the startup phase of the system based on the idea of intermittent charging of an on-chip capacitor. The circuit was simulated and implemented using the 0.18 μm BCD process. Simulation and test findings reveal that the soft-start time is 2 ms, the layout area occupied by the circuit is 0.018 mm², the soft-start circuit can suppress peak inrush current by up to 87.3%, reducing the inrush current to below 634 mA, and there is no overshoot in the output voltage. The proposed architecture does not consume system power and is fully integrated on the same chip without any external components, which effectively reduces the die size and the cost.

In order to improve the flexibility of the current protection circuit operation, a current protection circuit that can change the current limit value by adjusting the resistance value of the external resistor is designed. The load current is sampled using a sense-FET sensing circuit designed with an improved common-source common-gate current mirror, which reduces losses while ensuring the accuracy of the current limit value. The current is processed through two different branches to improve the efficiency of fault handling. The design is implemented using a 0.18μm BCD process. Simulation results show that at a supply voltage of 12V, current limit range of 1A∼5A, the accuracy is less than 0.96% affected by temperature, the fast shutdown time is about 70ns, and the completion of the protection time is about 1μs.

A high-efficiency power amplifier (PA) and a high-conversion-gain (G_C) upconverting mixer (UCM) were developed using 75-nm InP-based MOS HEMTs to enable sub-THz beamforming with a sufficiently large equivalent isotropic radiated power (EIRP) and effectively suppressed grating lobes. The chip sizes of both millimeter-wave monolithic integrated circuits (MMICs) were minimized to less than 1 mm, facilitating their integration into a sub-THz phased-array (STPA) transmitter with an antenna pitch of one wavelength or less, specifically less than 1 mm at 300 GHz. The PA MMIC demonstrated superior performance compared with conventional PAs in the 300-GHz band owing to advanced manufacturing technologies, including the use of a modulated passivation film alongside the gate oxide and epitaxial structures. A peak power-added efficiency (PAE) of 9.3% was achieved, with an associated output power of 9.2 dBm and a linear gain of 18.6 dB at 300 GHz. To the best of our knowledge, the achieved PAE is the highest reported to date. Moreover, the UCM MMIC, which comprised a third-order subharmonic resistive mixer, an on-chip band-pass filter, and an RF amplifier, operated with a 5-dBm local (LO) signal at 90 GHz. The MMIC demonstrated a high G_C of −1.9 dB, a 3-dB bandwidth spanning 39 GHz (270-309 GHz), and a 1-dB gain-compressed RF power of −10.4 dBm, with a power consumption of 84 mW. The observed 3LO leakage power was −26.5 dBm. These findings indicate that a higher EIRP can be achieved with reduced power consumption through the use of an STPA transmitter that integrates a Si CMOS IC and an InP-based MMIC based on the circuits described here.

This paper presents a circuit implementation of a dual-dither strategy that combines calibration dither and linearization dither to effectively address the correlation between calibration performance and input signal amplitude, while mitigating amplifier output compression and range redundancy caused by multi-level dither injection. Specifically, we propose the ‘Roving Star’ scheme, which generates a multi-bit, uniformly distributed, and uncorrelated dither signal. Additionally, we propose a threshold voltage dithering circuit with a wide-range adaptive adjustment reference voltage to correct residual curve deviation resulting from the mismatch between flash and multiplying digital-to-analog converter (MDAC) reference voltages. These advancements were successfully implemented in a 500 MS/s 14-bit pipelined ADC fabricated with a 40 nm CMOS process. The implementation resulted in significant performance improvements, notably increasing the SFDR from 69.4 dB to 89.2 dB and enhancing the SNDR from 65.6 dB to 70 dB.

This paper presents a design method aimed at enhancing the high-efficiency fallback range of ultra-high-power Doherty power amplifiers. This method integrates 27mm and 36mm gate-width chips into a dual channel device by optimizing the internal matching design. It employs an asymmetric design combining a power input ratio of 1:2 and a power ratio of 2:3 to extend the fallback range and minimize efficiency degradation. Additionally, an enhanced Π-type double impedance matching and fifth- stage post-matching design were proposed to address the limitations of narrowband performance. Finally, a 470W asymmetric Doherty power amplifier based on GaN HEMT was developed. The measured results indicate that within the 2.50-2.75 GHz frequency range, the amplifier achieves a saturated output power of 56.3-56.7 dBm, a linear region gain of 17.2-17.9 dB, and a saturated drain efficiency of 68%-73%. At an 8 dB power back-off, the drain efficiency ranges from 59% to 64%. This method presents an effective scheme for achieving a high-efficiency fallback range in ultra-high-power Doherty amplifiers.

With advances in CMOS technology, the threshold voltage variation has worsened, which has a bad impact on the timing variation for sense amplifier enable signal. This paper proposes an oscillator replica bitline (ORB) technique for suppressing timing variation of SRAM sense amplifiers. The number of MOSFETs used in the ORB technology is approximately 40% of that in conventional replica bitline technique and the ORB technique can be programmed to modify sense amplifier enable timing. The simulation results show that, at a supply voltage of 0.8V, the timing variation can be reduced by approximately 52.37% and 6.29% compared with the conventional replica bitline technique and replica bitline with multistage technique, respectively.

In this paper, a four-channel 14bit 10M/S TI SAR ADC with 1.8V power supply voltage and 1V reference voltage is implemented on the Cadence platform. At the same time, a calibration method based on fully connected neural network is proposed. After the error analysis of the designed ADC, the random mismatch is introduced to the capacitance array(CDAC) and the PVT combination simulation is carried out in the center frequency range of ±1% to obtain multiple sets of error data as network training data and test data. The back propagation(BP) algorithm is used to train the neural network until the network converges, 11 sets of data are input for testing. The test results show that the average effective number of bits(ENOB) and spurious-free dynamic range(SFDR) are improved by 4.72bits and 34.17dBc respectively after calibration, and the network also has a calibration effect on input signals other than training frequency.

Mel-frequency cepstral coefficients (MFCC), an FFT-based speech feature extraction (FEx) algorithm, is a significant power consumer in low-power keyword spotting (KWS) chips. This work presents a KWS chip with an energy-efficient FEx, with an expanded-3bit-twiddle FFT (E3bT-FFT) algorithm which reduces power of FFT by 5.7x. Meanwhile, a multiplier-free MFCC (MF-MFCC) is proposed, effectively eliminating power-hungry multipliers and reducing the MFCC computational load by 7.3x. Fabricated in a 65-nm CMOS process, the chip occupies 0.17 mm² and consumes 2.3 µW, with the computation unit in FEx consuming just 76 nW, and achieves 94.9% accuracy on a 1-Word KWS with Google Speech Commands dataset (GSCD).

This paper presents a 2.4 GHz receiver front-end employing a 3× passive subharmonic mixer and a polyphase filter (PPF) to achieve low power consumption. We proposed a new subharmonic mixing technique in this study to design the mixer. Given that the generation of multiphase local oscillators (LO) is challenging in passive subharmonic mixing, we proposed a new PPF that can generate the LOs at lower cost compared to previous works. Consequently, a standard LC oscillator can work in conjunction with this receiver front-end. This work is designed with 65nm CMOS technology and the post-simulation shows the power consumption of this receiver is 340 µW, noise figure is 6.27 dB and IIP₃ is -27.3 dBm.

Capacitive-type level transducers are widely employed due to the increasing demand for level monitoring in various industrial systems. Accurate modeling of these transducers is crucial for improving their measurement performance. This paper introduces an equivalent circuit model for capacitive-type level transducers that accounts for the internal edge effect, addressing limitations of traditional models, which often overlook the actual conditions between the inner and outer electrode bases. Furthermore, this paper proposes a novel analytical approach based on electromagnetic field analysis to characterize the internal edge effect. To validate the proposed model, a capacitive-type level transducer was fabricated, and performance was tested using several prototypes with varying distances between the inner and outer electrode bases, leveraging finite element method (FEM) simulations and experimental results.

Many electronic devices such as smartphones can now utilize wireless charging. Most of the power transmitting and receiving coils built into these devices are single-layer planar spiral coils to make them lighter and thinner. However, manufacturers have difficulty determining whether or not to wind the coil all the way to the center and what the inner diameter of the coil should be. In this paper, we clarify the various electrical and physical properties given by different inner diameters and present the optimal inner diameter ratio for power transfer efficiency. The analysis results show that the optimal inner diameter ratio for obtaining the maximum power transfer efficiency in the resonant frequency range of 100 to 200 kHz is 0.288 to 0.391 when the outer diameter is 43 mm.

This paper presents an all-MOS ring oscillator with a temperature compensation circuit, which can be integrated into a microcontroller unit (MCU) chip. We suppose a compensation circuit to mitigate the frequency drift caused by temperature fluctuations. The absence of resistors and capacitors in the oscillator can significantly reduce the layout area. In addition, the current-starved circuit minimizes power consumption and enabls flexible frequency adjustment. The design has been simulated using a 180nm CMOS process, resulting in a layout area of the oscillator less than 0.00495mm². Experimental results also demonstrate that the oscillator achieves a stable clock of 350MHz at a voltage-controlled input of 850mV. Furthermore, across the temperature range of -40℃ to 125℃, the maximum frequency variation remains between -0.88% to +0.297%. The oscillator’s power consumption is as low as 0.315mW.

A new zero space orthogonal projection (ZSOP) method is presented to synthesize the antenna array pattern. The expected pattern vector is divided into two parts, the main lobe vector and the side lobe vector. In order to maximize the side lobe attenuation, the optimal solution of the antenna element excitation vector should be placed in the zero space of the side lobe steering matrix. Therefore, the optimal solution of the antenna element excitation vector must be in the orthogonal projection space of the conjugate transpose matrix of the side lobe steering matrix. Thus, the pattern synthesis equation can be transformed into a new form. The solution of the new equation can ensure that the optimal solution of the antenna element excitation vector can form a pattern with an extremely low null beam level. Examples are used to demonstrate the advantages of the new method. Simulation results show that the new method can form patterns with excellent null beam levels that far exceed the performance of other methods. The new method can work with non-iterative calculation steps. It requires only slightly more computation amount than the traditional least square method to complete the pattern synthesis task.

Due to its simplicity in circuit implementation, conventional Data Weighted Averaging (DWA) is commonly used to calibrate capacitor mismatch in feedback DACs. However, for low-amplitude input signal, the non-random use of capacitor elements causes periodic mismatch errors, leading to harmonic distortion in the signal band. Consequently, this results in significant harmonic distortion within the signal band. This paper proposes a randomized DWA algorithm that utilizes the amplitude of the input signal to control the starting position of DAC elements for each cycle, thereby suppressing tones caused by DAC element mismatches. Compared to the conventional DWA algorithm, this approach achieves higher linearity while reducing DAC switching activities. To evaluate the proposed algorithm, a second-order discrete-time sigma-delta modulator model was designed. Simulation results indicate that the proposed algorithm achieves up to a 14% reduction in switching activities and extending the dynamic range by approximately 5 dB compared to the conventional randomized DWA algorithm.

Physical Unclonable Functions (PUFs) represent a promising hardware security technology, particularly under resource-constrained conditions. However, conventional Arbiter PUFs (APUFs) are highly vulnerable to machine learning (ML) attacks. To address this limitation, this paper proposes an innovative PUF circuit design scheme leveraging parallel delay arbitration. The approach involves constructing a two-tiered APUF architecture, where the delay differences of individual path segments are extracted for arbitration. The final PUF response is obtained by XORing the arbitration results, thereby enhancing the linear complexity between the circuit's challenges and responses. This significantly improves the PUF's resistance to ML-based attacks. Experimental results demonstrate that even with a training set comprising 10⁶ challenge-response pairs and employing various ML models for attacks, the prediction accuracy remains substantially lower than that of a 3XOR-PUF with comparable hardware resource utilization. Moreover, the proposed PUF circuit exhibits excellent performance across other critical metrics, achieving a stability of 98.03%, while maintaining nearly 50% randomness and uniqueness.

To improve the performance of the boost circuit, a fuzzy inference systems (FIS) design method based on adaptive neural networks (ANN) system identification is proposed for the boost circuit. Using ANN for system identification based on training data to generate initial first-order Takagi—Sugeno (T-S) FIS. Adjust the FIS parameters by comparing them with the testing and checking data, and iterate until the error is within an acceptable range to form the final FIS. The steady-state and dynamic capabilities of the boost circuit under FIS control have been verified through simulation and experiments to be superior to traditional proportion integral differential (PID) control. The experimental results show that when the input voltage jumps from 28V to 22V, the boost speed of the boost circuit based on FIS control is improved by 21.5% compared to PID.

In this paper, we propose a novel MIMO-enabled integrated sensing and backscatter communication (MIMO-ISABC) system to serve multiple users, and focus on the transmit beamforming design for the system. Under the total transmit power constraint, we aim to design sensing and communication beams that meet both tag detection and communication requirements. First, we use minimum mean square error (MMSE) beamforming to design the beamforming vectors, followed by convex optimization to allocate power between sensing and communication. Then, we investigate a joint beamforming optimization problem to minimize the total transmit power while meeting the tag detection and communication requirements. To solve this, we transform the non-convex constraints into convex second-order cone constraints. The experimental results demonstrate the validity and performance of the proposed scheme and associated algorithms. The proposed MIMO-ISABC system offers great potential for applications in IoT scenarios.

Junction temperature calibration of power devices is important for estimating the junction temperature. In this paper, a pulse-current calibration method is proposed as a means of improving the efficiency of temperature calibration, utilizing the on-state voltage of SiC MOSFET as a calibration parameter. Firstly, the junction temperature calibration platform is constructed and a suitable parameter acquisition system is implemented. Subsequently, the corresponding calibration strategy and experimental flow are proposed, and the calculation of bus capacitance and inductance is given. Ultimately, the self-heating of the SiC MOSFET during the calibration is evaluated quantificationally. The results demonstrate that the self-heating effects associated with the proposed calibration method are negligible, thereby confirming the feasibility of the proposed strategy. Furthermore, the method is capable of acquiring a substantial amount of data in a single experimental test, which markedly enhances the efficiency of the calibration process.

There are a large number of 2.45G weak energy signals in the environment, which can be collected and realized for applications by microwave wireless energy transfer systems (WMPT). However, the rectification efficiency of WMPT with Si MOSFET as the core rectifier component is low at 2.45G weak energy density. In this paper, a high carrier mobility composite strain GeOI material is proposed and designed, and the optimal crystal orientation/crystal plane of the composite strain GeOI PMOSFET channel is optimized and determined by quantum mechanics related theory. The GeOI PMOSFET device is simulated and designed using Silvaco software, while a half-wave rectifier circuit with a load of 0.5pf and 30kΩ is built in the Mixed-mode module, and its peak rectification efficiency can reach 42.1% at 3.89dBm. The rectification efficiency at -12.1dBm 2.45G weak energy density reaches 6.5%, which is 3.96 times higher than that of the equivalent body Si MOSFET.

This paper presents a SerDes receiver for medium-reach interconnection in a 28-nm CMOS process. It employs a CTLE and an adaptive quarter-rate loop-unrolling 5-tap DFE utilizing an SS-LMS algorithm to enable adaptive adjustment of tap coefficients under different channels. The proposed DFE contains CML-based summer with CMFB technology and two-stage dynamic comparator with an offset calibration loop. Simulation results show that this receiver can operate at 25 Gb/s data rate with a power efficiency of 5.99 pJ/bit, Its BER is less than 1E-12 and eye-wide-opening is 0.67 UI under 20.6-dB channel loss at 12.5 GHz Nyquist frequency.

This brief presents a 0.18-μm BCD low-dropout regulator (LDO) designed for low-power Internet of Things (IoT) devices that achieves fast transient responses with a nA-level quiescent current (IQ) and operates without external capacitors. The power supply voltage can be reduced to 0.9 V, consuming only 284 nA of quiescent current. The design incorporates an adaptive bias and a class-AB OTA with dual Gm stages, achieving low IQ. Its second stage forms a feedforward path, utilizing only a 2 pF compensation capacitor. The combination of this feedforward path and an FVF buffer with body bias modulation enables zero-point load tracking compensation technology, ensuring loop stability under light loads in this capacitor-less LDO. Moreover, reducing the size of the pass transistor MP minimizes the overall area of the LDO to just 0.005 mm². An FVF buffer integrated with a comparator-based transient enhancement circuit improves the LDO's transient response. Post-simulation results demonstrate a load regulation of 0.0974 mV/mA, and a superior transient figure-of-merit (FOM) of 1.14-fs.

In this paper, an Efficiency Optimization Strategy (EOS) is proposed to address the issue of low efficiency in the Dual Active Bridge (DAB) DC-DC converter across certain power ranges under wide voltage conditions, with the aim of further enhancing the converter's efficiency over a broad operating range. First, in the low power range, a phase-shift control strategy is introduced, which enables wide-range Zero Voltage Switching (ZVS) and near-optimal inductor current RMS values. Through this strategy, ZVS is ensured for all switches under light load conditions, while under medium load conditions, ZVS is lost for only two switches. Subsequently, in the high power range, the optimization target is smoothly transitioned to the optimal RMS current value by utilizing the natural ZVS characteristics of the DAB converter. The operating range of the EOS is effectively extended, further reducing current stress and RMS current values, thereby achieving global efficiency optimization of the DAB converter. Finally, an experimental platform is constructed for verification, and the correctness and effectiveness of the theoretical analysis are confirmed by the experimental results.

A low-power, fast-response transmitter based on frequency-shift keying (FSK) is presented and used in the Sub-GHz band. This transmitter uses the closed-loop modulation structure of a phase-locked loop (PLL) and maintains the constant loop bandwidth of a PLL to ensure a consistent data rate at each frequency point of Sub-GHz. A fast and accurate VCO frequency sub-band selection technology is proposed to reduce the selection time of the optimal variable capacitor array control bits of VCO, thus improving the response speed of PLL and transmitter. This transmitter is implemented in the SMIC 0.18 μm CMOS process. The measured results showed that the selection time of the optimal VCO frequency sub-band is only 3.04 us, and the Error Vector Magnitude (EVM) of the whole transmitter is 4.17% at 115 kHz data rate, meeting the wireless transmission requirements of the nodes of Internet of things.

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the high-speed clock ensures the high precision of the synthesized timing signal without the need for calibration. The reconfigurability of the clock resources provides the DTC with variable resolution and enhanced flexibility for various applications. Based on this approach, a multifunctional DTC is designed to offer both timing sequence and random timing signal functionalities, catering to a wide range of application scenarios. The timing sequence function generates a continuously variable timing signal stream, while the random timing signal function produces random signals with uniformly distributed time intervals. Experimental results, using a Xilinx Kintex-7 FPGA, validate the effectiveness of the proposed methodology. The system achieves a resolution of 100 ps, a dynamic range from 1 ns to 40 μs, a DNL of -0.02/0.02 LSB, an INL of -0.04/0.03 LSB across the entire range. This approach can be readily adapted to various high-precision timing signal applications.

This article presents a novel low dropout regulator with high PSR and reliable stability. In order to achieve high PSR, this design use PSR enhance circuit to filter the voltage ripple from reference at low frequency, and achieving -82dB PSR at 1KHz with the load of 20mA. Besides, owing to the dynamic RC compensation network, this design can reconfigure the compensation resistor and capacitor, and achieve good stability at full load up to 250mA. Finally, this design was implemented with the 0.5-m CMOS technology, and the total quiescent current of the proposed LDO is only 12A.

In modern system on a chip (SoC), input/output (I/O) devices typically utilize direct memory access (DMA) and access virtual memory in the regular way. Additionally, operating system (OS) tends to allocate physical I/O memory contiguously. To reduce latency overhead due to page-table walks, hardware often employs translation lookaside buffer (TLB) prefetch techniques. Recently, TLB coalescing schemes that merge contiguous pages into a TLB entry have been reported. However, the conventional TLB prefetchers operate in the page level and do not effectively leverage the advantages of contiguous allocation. In this paper, we present the TLB prefetcher that exploits both contiguous allocation and TLB coalescing for I/O devices. The presented prefetcher operates in the block level, exploits contiguity in memory, requires no history tracking schemes, and can reduce page-table walks compared to the conventional scheme. Our experiments indicate that the presented scheme can improve both TLB and I/O device performance.

Analog computing-in-memory (ACIM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, inefficient analog-to-digital converters (ADC) will inhibit the performance improvement of this system. The primary contribution is in two aspects. First, we present a weight-flip-store coding technology that reduces the ADC resolution by one bit while maintaining the inference accuracy. Second, we propose a readout mechanism that can adaptively choose to skip high three-bit quantization cycles depending on input sparsity, further reducing ADC power. The experimental results show that the ADC power can be reduced by 28.5%-44.4%.

This paper presents a highly integrated, relatively high data rate wake-up receiver (WuRX) designed and implemented in 65nm CMOS technology. The receiver operates at 2.4 GHz band and exhibits robustness against power supply variations, and achieves a data rate of 20kbps. It employs a sub-threshold enhanced differential structure for the envelope detector to enhance noise performance and a bias-free baseband amplifier to improve the sensitivity. Operating at a nominal voltage of 0.5V, the WuRX consumes just 98nW and achieves a sensitivity of -62.8dBm.

In digital DC-DC converter systems, factors such as noise, line mismatches, process variations between chips, and common mode level shifts can cause the overall system output voltage to deviate from expectations. This paper proposes a code-search-based accuracy calibration technique for the delay line based ADC in digital DC-DC converter system. By adjusting the calibration module and automatically searching for the maximum output code value, this technique effectively enhances the quantization accuracy of the ADC. The overall chip is fabricated using 0.18 μm CMOS technology, and the ADC occupies an area of 750 μm × 940 μm. Experiment results demonstrate that this technique can improve the ADC's quantization accuracy to 94.7% and reduce the overall DC-DC loop offset from 2.8% to 0.2%, significantly enhancing the accuracy of the DC-DC output.

In this study, we present a method for filling molten solder into through-glass via (TGV) substrates using a pulse width modulated (PWM) vacuum suction system. The TGV substrates were fabricated using micro-electro-mechanical systems (MEMS) techniques, incorporating anodic bonding and glass reflow processes. The vacuum suction system comprises a vacuum chuck, pressure sensor, pulse control circuit, and solenoid valve. The solenoid valve modulates the vacuum level of the chuck by opening and closing. The switching frequency was set to 1 Hz with a 20% duty cycle. TGVs were fabricated in the glass substrates with diameters of 150 μm and thicknesses of 350 μm. The vacuum filling yield was approximately 30% at 40 kPa and exceeded 98% at 80 kPa vacuum level. X-ray imaging confirmed void-free filling results. The individual via resistance of the tin-filled TGVs was measured at 69.8 ± 38.5 mΩ using the four-probe method.

While CNT FETs have been demonstrated to exhibit excellent resistance to irradiation, the radiation effects in complex environments remain relatively understudied. This paper investigates the synergistic effect of CNT FETs under the combined action of ionization and displacement damage using proton irradiation. It was observed that the V_th degradation (0.06 V) induced by 40 MeV protons was twice that (0.03 V) induced by 70 MeV protons with the same ionization dose. The numerical simulations indicated that the 40 MeV proton irradiation results in the formation of displacement defects in closer proximity to the semiconductor channel. This increased the hole capture rate, leading to a higher concentration of fixed charge in the SiO₂ layer and a larger threshold voltage shift.

In this work, gate leakage behavior on Schottky-type p-GaN gate AlGaN/GaN HEMT is investigated, especially when the Schottky junction is damaged. A controllable degradation of the Schottky junction is achieved, then the previous semi-floated p-GaN is electrically connected to the gate electrode. Therefore, the pre-stressed GaN device exhibits an improved gate stability, as well as a normal gate control and large gate swing. Furthermore, the associated trap level is extracted by Arrhenius plot based on the exponential relationship between the recovery speed versus temperature.

This paper proposes a voltage-controllable switched reluctance generator (SRG) system with a ring winding structure driven by a full-bridge power converter, which is the first application of a full-bridge power converter to drive the SRG. The proposed topology inherits the advantage of low copper loss of the ring winding that combines AC and DC currents together. It connects the equivalent DC power provided by a DC-DC half-bridge circuit to the ring winding to provide circulating DC and partial excitation energy. This paper provides a detailed description of the proposed system's feedback loops and operating principle. The proposed topology is compared with the uncontrollable Circulating-Current-Excited Switched Reluctance Generator (CCEG). The comparative study is validated through simulation and experimental platform, and the results highlight the output voltage performance of the proposed topology and control method.

Swimming is one of the most popular worldwide sports, which offers the players healthy body, improved fitness, and endless enjoyment due to its easy accessibility and year-round availability. Monitoring swimmers can aid in the development and participation of swimming sport. However, due to the difficulty of in-water monitoring, the existing methods in tool box are still limited. In this paper, a more accessible wearable monitoring system based on a flexible piezoelectric device is developed. This system collects muscle contracting and relaxing information by measuring its generated force on a Polyvinylidene fluoride (PVDF) sensor. Then the information is transmitted via a low-frequency radio frequency (RF) signal to the receiver on land. This information is analyzed using a convolutional neural network and the classification of different strokes is realized. The system also supports monitoring at two positions by wearing multiple devices on the body. By integrating data from multiple positions, the analysis algorithm achieves a higher prediction accuracy of over 95%. This work demonstrates that the combination of wearable monitoring devices, the Internet of Things, and Artificial Intelligence, which holds significant promise for sports education, research, promotion, and development.

This paper presents a transparent super-wideband (SWB) MIMO antenna based on a metal mesh structure. The metal patch and substrate of the antenna are hollowed out, resulting in a transparency of up to 77% and a radiation efficiency exceeding 82%. The bandwidth of this MIMO antenna ranges from 1.6 to 19.2 GHz, achieving a bandwidth ratio of 12: 1. An engineered parasitic decoupling structure ensures that the isolation between antenna elements is greater than 25 dB, and the envelope correlation coefficient (ECC), diversity gain (DG), channel capacity loss (CCL), and total active reflection coefficient (TARC) all reach good values.

In this paper, an improved coverage optimization method for video sensor networks(VSNs) based on Whale optimization algorithm (SGWOA) is proposed to solve the problem of uneven distribution of nodes in random deployment of video sensor networks, which will cause coverage holes or coverage redundancy in the coverage area of VSNs. Firstly, Sobol sequence is used to initialize the population, which improves the diversity of the population and makes the distribution of network nodes more uniform when randomly deployed. Secondly, the nonlinear convergence factor and adaptive inertia weight are introduced to prevent the algorithm from falling into local optimal prematurely. Finally, Levi's flight strategy is added to disturb the position update during whale optimization, which speeds up the convergence of the algorithm and avoids premature convergence.

This study develops new technology for detecting metal foreign objects to enhance the safety of wireless charging systems. The intrusion of metal objects during charging may result in reduced performance, increased energy consumption, and excessive heat generation, which may potentially damage the charging system. In this paper, we develop an innovative sensorless method of detecting foreign objects. We build an efficiency model by conducting experiments with metal objects of various sizes placed between charging coils. This approach identifies metal objects on the basis of efficiency changes, eliminating the need for sensors, thus effectively reducing costs. Finally, the effectiveness and reliability of this model are validated using the experimental platform.

An application dependent FPGA interconnect testing scheme is presented. The goal is to reduce the number of test configurations while keeping high fault coverage. Reduction is done by using SMT constraints that allow multiple nets as a group to use one input vector, so that the number of test configurations is reduced. Based on the complete fault model, a novel approach to generate SAT formulas, most notably dominant bridging faults, are explained to retain coverage. Experiments on FPGAs shown that this method yield on average 44% fewer configurations on circuits with 1000∼100000 LUTs comparing with existing methods, with full fault coverage.

Due to the low noise and high linearity characteristics of GaAs Hetero-junction Bipolar Transistors (HBTs), Low Noise Amplifiers (LNAs) are widely used in aerospace, communication, computer, and other fields. Extracting device model parameters is of great significance for subsequent research on the electromagnetic compatibility characteristics of such devices. In this paper, based on the small signal model, the model parameters of the amplifier are extracted by combining the I-V characteristics of the amplifier under different external voltage conditions. The linear model parameters are extracted using a fitting analysis method to obtain the Pspice circuit model of the GaAs amplifier under normal operating conditions. The simulation results align closely with the measured results. Compared with traditional modeling methods, this approach effectively resolves the issue of being unable to measure parameters due to chip packaging. This method holds substantial significance in extracting circuit model parameters and conducting in-depth research on circuit electromagnetic compatibility characteristics of this device.

This paper presents a bandgap reference (BGR) circuit with high precision and low power, which is suitable for wide supply and temperature range DC-DC converters. A thermal compensation method is designed to improve output accuracy. A thermal shutdown detection (TSD) circuit is proposed to prevent overheating. It also adopts a two-channel pre-regulator, which reduces the current consumption and area while enhancing PSRR. The measured results show the temperature coefficient (TC) stands at 5.69 ppm/°C in the range of -40°C to 155°C. The typical current consumption is 0.84μA in the supply range from 3.5 to 40 V. The PSRR is -86dB at 1kHz.