A wideband crossed dipole antenna for dual-polarized applications is presented in this paper. The antenna consists of a printed crossed dipole radiator loaded with periodic slots, four metal posts, four metal sidewalls and a metal reflector. The crossed dipole antenna is directly fed by a simple coaxial cable, achieving stable dual-polarization radiation characteristics. Here, two approaches are adopted to adjust the high and low resonant frequency of the antenna with large freedom. Firstly, four metal posts are introduced into conventional crossed dipole antenna, and their distance from the feeding point can independently adjust the lower resonant mode. Secondly, periodic slots are etched on the crossed dipole arms, and the upper resonant frequency can be controlled independently by altering the length of these slots. Also, the metal sidewalls on the ground are used herein to obtain enhanced gain property. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The measured results show good performance of a relative bandwidth of 64.3% for VSWR ≤ 2 (1.32-2.57 GHz). Moreover, the antenna has good unidirectional radiation performance and can achieve maximum gain of 9.1 dBi at 2.3 GHz.

For general metallic cavities, the overmoded frequency is of critical for electromagnetic applications. In order to estimate the overmoded field behavior without a mechanical stirrer rapidly, a simple scattering parameters measurement-based procedure is presented, on which the samples will be obtained by mean of hybrid stirring technique, e.g., frequency and source stirring strategies. Then, the correlation analysis and coefficient of variation are used to deal with the samples, aiming to estimate the overmoded frequency. A comparison has been made between the results estimated by hybrid and mechanical stirring-based method, which highlights that the hybrid stirring-based method can be regarded as an alternative solution for mechanical stirring.

This paper introduces a novel balanced bandpass filter that utilizes the symmetrical F-shaped groove (SFG) substrate-integrated waveguide and spoof surface plasmon polariton (SIW-SSPP) structure. This design combines lowpass SSPP unit cells within a highpass balanced dual-layer SIW structure to realize bandpass filtering response. The SFG SIW-SSPP unit cell’s superior dispersion properties contribute to broad bandwidth and extensive stopband. Additionally, the balanced dual-layer SIW structure, achieved by removing a rectangular aperture from the common ground, allows for high in-band common-mode (CM) suppression and a broad CM suppression range. The proposed filter offers multiple variables to regulate the passband’s lower and upper cut-off frequencies independently. A fabricated prototype of the balanced filter is tested, demonstrating superior performance compared to previously reported balanced SIW and half-mode SIW BPFs. The filter achieves a broad 3-dB fractional bandwidth of 46.55% (6.33-10.17 GHz), a wide 20-dB stopband rejection up to 2 f₀ (f₀: the passband’s center frequency), and simultaneous broad CM suppression range (24-dB up to 4.85 f₀).

A geometric structure model method has been proposed to provide more non-isolated step-up DC-DC converters and improve the existing topology derivation methods. Based on the three existing DC-DC converters, a geometric structure model is constructed. According to different connection relationships and components represented in the model, ten new high step-up converter topologies are derived. A group of topologies consisting of four DC-DC converters is taken as an example, and a superior converter, namely the high-boost switching inductor converter, denoted as HB-SL converter, is obtained through characteristic comparison. Furthermore, the voltage gain, voltage stress and component parameter design criteria of HB-SL converter are given, and the effectiveness of HB-SL converter is verified by experiments.

This paper proposes a high-efficiency wideband continuous-class power amplifier (PA) optimizing the fundamental and harmonic impedance areas to achieve wideband and efficient operation. Unlike conventional impedance area constraint methods, reflection coefficient circles are used to characterize the desired fundamental and harmonic impedance areas, thereby increasing the number of feasible solutions in the output matching network (OMN) optimization. Additionally, a multi-objective algorithm is employed to optimize the OMN, enabling the PA to achieve high efficiency over wide frequency band. To validate the feasibility of the proposed method, a continuous-class PA operating in the frequency range of 1.5-2.6 GHz is designed and measured. The results demonstrate that the PA achieves a saturated output power of 40-41.5 dBm with a corresponding gain around 10 dB. Maximum efficiency ranging from 68% to 75% can be achieved within the operating frequency range.

We have investigated a magneto-optical (MO) isolator fabricated by µ-transfer printing (µ-TP) method which enables tiny bonding area with a low-temperature process. Although excessive absorption loss can be reduced, the large junction loss at the boundaries of MO material cladding is still a problem. We propose two ultra-low-loss Mach-Zehnder interferometer-type MO isolators. The tapered coupon type isolator reduces the junction loss of TM mode. The TE input type isolator reduces the junction loss by propagation of TE mode instead of TM mode. We designed these structures and numerically demonstrated ultra-low-loss isolators with insertion losses of <2 dB.

In this paper, we propose a novel methodology for designing a rectifier with wide input power range (WIPR). In the proposed structure, a two-port resistance compression matching network (RCMN) is employed to extend the dynamic range of the input power. Generally, resistance compression network (RCN) is developed based on three-port network theory. This leads to the conventional RCN-based rectifier has two sub-rectifiers and arranged in a dual-branch topology. Compared with the conventional RCN-based rectifier, the proposed two-port RCMN-based rectifier not only has a single-branch topology but also can work without using an individual impedance matching network. Thus, a compact size and lower circuit complexity can be achieved. The closed-form design equations of the proposed two-port RCMN are designed. For validation, a 2.45 GHz WIPR-rectifier prototype is fabricated and tested. The experimental results show that the power convert efficiency (PCE) is higher than 50 % when the input power varies from -2.1 to 13.1 dBm. The peak PCE is 74.5 % with a 10.2 dBm input power. And its physical size is only 43 mm × 24 mm.

In order to solve the problems of the traditional model reference adaptive system (MRAS) speed estimation adaptive mechanism, such as poor tracking accuracy and slow response, A new dual sliding mode adaptive observer is designed to estimate the rotational speed and rotor position of permanent magnet synchronous motor (PMSM). Firstly, a new two-variable complex reaching law is used to replace the traditional first-order sliding mode for velocity loop control, and an anti-saturation scheme is introduced to improve the anti-interference ability of the system. Secondly, the PI adaptive mechanism in the traditional MRAS is replaced by a new super-twisting weighted integral type algorithm adaptive observer (STWITA-AO), which effectively speeds up the convergence of the estimated speed and reduces the inherent chattering of the sliding mode structure. Finally, the relevant simulation is compared and verified. The simulation results show that the estimation strategy based on the new double sliding mode MRAS control can make the speed estimate converge to the actual value faster, and improve the dynamic performance and robustness of the observer.

A modified Wilkinson power divider (PD) with improved in-band performance and compact size is proposed in this paper. Compared with conventional Wilkinson PD, such structure features with an additional shorted stub on the output port, which can introduce an extra transmission pole for in-band performance enhancement. Besides, the proposed Wilkinson PD adopts meander line for compact size. Furthermore, the isolation resistor is achieved with thin film resistance technology to avoid welding tolerance. To verify the mechanisms mentioned above, a modified Wilkinson PD operating at 7 GHz is designed and fabricated in size of 8.2mm×8.8mm (0.2×0.19), with significantly benefit of compact, wide-band, low loss and well in-band loss flatness characteristic. The measured fractional bandwidth (FBW) is 57.1% (i.e., 5-9 GHz) with insert loss of 3.2-3.4dB. Meanwhile, the return loss is less than 15dB.

A method is proposed for a hybrid power supply modulator (PSM) which consists of a wideband linear amplifier (LA), switching converters (SC), and a hysteresis comparator (HC) for an envelope tracking transmitter. By a compensation method of using a dual feedback network, the stability of the LA circuit is realized. A System in Package (SiP) structure based on separated gallium nitride (GaN) devices and the designed LA is proposed to achieve high performance, high reliability, and miniaturization. Ranging from -40 ∼ 100℃ of operating temperature, the 3dB bandwidth of the proposed PSM can reach over 120MHz which achieves the maximum efficiency of 82% at an average output power of over 4W with 2.5 ∼ 4.5V power supply. Using a long-term evolution (LTE) 10MHz quadrature phase shift keying (QPSK) with Peak to Average Power Ratio (PAPR) of 6.5dB at 225 ∼ 512MHz, the envelope tracking transmitter is measured that the power added efficiency (PAE) is 58.95 ∼ 66.96%, Error Vector Magnitude (EVM) is 1.7 ∼ 2.36%.

With the widespread use of electric vehicles, the large disturbance caused by the uncertainty of the AC side of the power grid will adversely affect the voltage stability of the DC side of the charging pile, which will threaten the charging safety of electric vehicles. In order to achieve fast and adaptive DC voltage regulation under large disturbance, this paper proposes a dual active bridge (DAB) converter control strategy based on Kalman Filter (KF) and Model Predictive Control (MPC). The improved Euler method is used to obtain a more accurate DAB discrete model, and the MPC control system is designed to improve the control accuracy. The best observation results of KF are used as feedforward compensation to improve the accuracy of output voltage regulation and ensure the stability of electric vehicles in the face of various disturbance problems. Finally, the effectiveness of the control strategy is verified by experiment.

In modern surgery, microwave surgical energy devices are used for hemostasis and anastomosis. However, elongated heating region called backward heating distributes around the feeding line, and potentially causes undesirable heating to non-targeted, normal tissue. In order to suppress the backward heating, we considered use of a sleeve with microwave device. Large sleeve inner diameter is required to use the sleeve effectively. However, small sleeve inner diameter is preferable for use in surgery. In this study, numerical analyses were performed to investigate the optimum sleeve inner diameter. The results indicated over 4 mm inner diameter could suppress the backward heating.

In this study, a novel active disturbance rejection controller (ADRC) is proposed to significantly improve the speed control performance of permanent magnet synchronous motor (PMSM). The conventional ADRC, namely linear active disturbance rejection controller (LADRC) and nonlinear active disturbance rejection controller (NLADRC), both them have their own merits and drawbacks. Thus, an enhanced switching active disturbance rejection controller (ESADRC) is developed to counteract the impacts of the speed-loop for the PMSM. The proposed ESADRC comprises several novel components including a novel tracking differentiator (TD), a novel switching extended state observer (SESO), a novel switching state error feedback (SSEF), and a cascaded extended state observer (ESO). The cascaded ESO is responsible for estimating the remaining disturbance after the SESO. Through comparative verification, it is verified that the proposed ESADRC outperforms the traditional ADRCs in terms of performance.

A capacitor-coupled stacked-based sense amplifier (CC-STSA) is proposed to compensate the input-referred offset voltage (V_OS), which dictates the minimum required bitline swing for a reliable read operation of static random access memory (SRAM). The data-aware coupled capacitors are employed to dynamically tune the driving ability of sensing transistors according to the data supposed to be read, thus improving the offset tolerance of sense amplifier (SA). Compared with the conventional current latch-type SA (CLSA), the simulation results in 55-nm CMOS technology show that the proposed scheme achieves more than 4.17X of the standard deviation of V_OS (σ_OS) reduction across the range of supply voltage from 0.6V to 1.2V and reduce the read energy consumption and read delay to 54.9% and 45.5% respectively. Furthermore, the proposed scheme reduces the σ_OS by 2.19X compared to DIBBSA on average.

In this letter, a high-efficiency 2.45 GHz class-F voltage doubler rectifier is proposed for radio frequency energy harvesting (RFEH). In the proposed topology, two harmonic termination circuits are employed to shape the current waveform to half sine wave and voltage waveform to square wave by yielding short termination at even harmonics and open termination at odd harmonics. Compared with previous class-F voltage doubler rectifiers, the proposed rectifier achieves a higher RF-DC power conversion efficiency (PCE). To validate the proposed approach, a 2.45 GHz voltage doubler rectifier has been designed and implemented. The measurement results show that the peak RF-DC PCE is 76% with a 15.6 dBm input power range. In addition, the measured PCE is higher than 50% over the input power range from 2 to 18 dBm.

In this paper, a 4.5-5.5 GHz wideband high efficiency Doherty power amplifier (DPA) MMIC using a novel compensation technique is proposed. The phase difference and output capacitances of the carrier and peaking PA are analyzed and compensated accurately in a wideband. Thus a sufficient load modulation of the DPA is obtained in a broadband. To verify the proposed design methodology, a broadband high-efficiency DPA MMIC is designed and fabricated in a 0.25 µm GaN-HEMT process for 5G massive MIMO applications. The measurement results illustrate that power added efficiency (PAE) is 44.8%-52.2% at the saturated output power (P_sat) of 39.8-40.8 dBm, the PAE at 6-dB output back-off (OBO) is 40.9%-43.9%, and the small-signal gain is 12.5-13.9dB. The proposed DPA demonstrates state-of-the-art saturated and 6-dB back-off PAE among published C-band broadband GaN MMIC DPAs.

This paper presents a high-precision, low-power CMOS temperature-to-digital converter (TDC) for detecting MEMS reference frequency sources on-chip temperature. This TDC uses a bipolar transistor as the core device for temperature measurement and a second-order Sigma-Delta ADC to read the temperature information. In order to improve the accuracy, the PTAT bias circuit with finite current gain compensation resistor and Dynamic Element Matching (DEM) circuit with Bank-Swap structure is employed in the temperature front-end circuit, respectively. In the ADC design, Analog T- switches (AT-Switch) with complementary structures are employed to reduce the leakage current of MOS switches in a fully differential switched-capacitor integrator to improve the accuracy further. Implemented in TSMC 180nm CMOS, the TDC occupies 0.135mm². The measurement results show that the average power consumption of the circuit is 95µW (@27°C) at a supply voltage of 1.8V. After temperature curve fitting, an inaccuracy of ±0.85°C(3σ) is achieved from -40°C to 85°C, which meets the requirements of the FBAR(Flim Bulk Acoustic-wave Resonator) oscillator for temperature compensation.

This letter presents a new microstrip diplexer with self-packaged and wide bandwidth based on substrate-integrated suspended line (SISL) technology. Diplexer consists of D-CRLH filters which include mixed coupling. The electromagnetic interaction is canceled out in the filter, generating two transmission zeros and giving the filter good stopband suppression. Diplexer utilizes a T-junction to make filters work in parallel. Each channel filter can be individually controlled. To validate the proposal, a diplexer operating at 1.88 GHz and 2.64GHz with fractional bandwidth (FBW) of 14.6% and 19.1% is designed and fabricated. A good agreement is perceived between measured and simulated.

In this letter, a second harmonic suppressed millimeter-wave (mm-wave) gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) power amplifier (PA) using the self-resonate characteristic of the capacitor is proposed. Based on a simple modified band-pass output matching network, a novel second harmonic suppression method by utilizing the self-resonate characteristic of the on-chip capacitor is proposed, which can realize the harmonic suppression without any additional tuning structures. For verification, a 24-to-28-GHz GaN MMIC PA was designed using a 150-nm GaN on silicon carbide high electron mobility transistor process. The fabricated PA achieved a saturated power range of 32.5-34 dBm, with a corresponding power-added efficiency (PAE) of 37.5%-44.5%. The amplifier achieved good linearity when excited by a 400-MHz orthogonal frequency division multiplexing signal after applying digital predistortion.

This brief introduces an area-efficient AdderNet hardware accelerator. AdderNet replaces multiply-accumulate computations of neural network processing with addition operations, thereby reducing computational cost. However, the previous accelerator uses two adders for a kernel computation to implement an absolute value computation, which still has circuit redundancy. For the efficient AdderNet acceleration, we propose a reconfigurable kernel unit and merged adder tree structure to relax such a computational circuit overhead. The proposed merged adder tree reduces the computing area by 23-28% compared to the state-of-the-art AdderNet hardware architecture.

As autonomous driving technology advances, the requirements for object detection are becoming increasingly high. Non-maximum suppression (NMS) algorithm, as a key component in traffic object detection algorithms, is an independent post-processing process in the object detection framework. Due to the complexity of real-world road scenarios and high density of detected entities in urban traffic, the number of candidate bounding boxes generated by the neural network is large. Hence, low-precision processors may generate a significant number of redundant target bounding boxes. The excessive output of redundant target bounding boxes not only imposes a workload on subsequent processing but also has the potential to result in non-optimal decision-making. We propose a high-performance NMS processor that can quickly process a large number of candidate boxes without performing sorting of their scores. Also, it has low precision loss computing units and high parallel computing arrays. Combined with algorithm design, it effectively reduces the computational complexity and reduces the inference time of the end-to-end task of the NMS algorithm. Thus, our NMS processor’s speed is comparable to SOTA architecture, and the average accuracy loss is only 0.4% .

This study focuses on the improvement of the performance of high-frequency current transformer (HFCT) for Partial Discharge Measurement and thus reveals a new design method of HFCT. An annular nickel-zinc ferrite is used as the magnetic core of the HFCT, and the parameters such as the number of winding turns and the diameter of the enameled wire are optimized. To test the HFCT, an experimental test platform is built according to the technical specifications of high-frequency partial discharge charged detection equipment. The test contents of the HFCT include transmission impedance, sensitivity, anti-interference characteristics, etc. The test results show that the new HFCT has a good response performance from 1MHz to 25MHz, the maximum transmission impedance value can reach 16.4mV/mA, the apparent charge of 5pC can be measured and signal-to-noise ratio is greater than 2:1. In addition, the designed HFCT also has good anti-interference and stability. With the self-designed low-power portable high-voltage cable insulation tester (mainly including signal conditioning circuit and data acquisition circuit), in the high-voltage laboratory, built a simulated discharge experimental circuit on the plate-pin, ball-ball two discharge models for high-voltage testing, the use of the developed HFCT to detect the partial discharge of the insulating polyethylene medium. The test results show that the HFCT can detect the partial discharge pulse signals before breakdown, with accurate data and reliable performance.

The previous PLC E₃₁ and E₁₃ mode converters employ linear tapered structures to fulfill the adiabatic coupling condition and achieve a high mode conversion efficiency, which requires long taper lengths. In this paper, we propose two types of PLC tapered structures that can be applied in different scenarios using fast quasiadiabatic dynamics. These structures enable mode conversions of E₃₁-E₁₃ modes, as well as E₃₁-LP₀₂ and E₁₃-LP_21b modes, respectively. The E₃₁-E₁₃ mode converter can be reduced from the previous three-stage linear taper of 12000 μm to approximately 4000 μm in length. Similarly, the E₃₁-LP₀₂, E₁₃-LP_21b mode converter can be reduced from the previous two-stage linear taper of over 6000 μm to approximately 4000 μm in length.

This letter presents a broadband compact watt-level high-efficiency power amplifier (PA) in 0.35-μm SiGe BiCMOS process. A four-way triple-tank-based power combiner is introduced and theoretically analyzed in detail with the consideration of the undesired inductor in the third tank. The coupling coefficient and the uncoupling resonant frequencies of the tanks can be adjusted to compensate for the deterioration caused by the undesired inductor, achieving broadband and low-loss matching. The proposed PA operates over 4.4-6.4 GHz and exhibits a peak gain of 35.2 dB, a maximum saturated output power (Psat) of 30.5 dBm, and a peak power added efficiency (PAE) of 34.8% at 5.4 GHz.

A low phase noise low power ring voltage-controlled oscillator (Ring-VCO) is proposed for phase-locked loops (PLLs) in the 802.11ah communication protocol band. A three-stage Ring-VCO with dual-path structure delay cells is designed to meet the high performance requirements of Internet of Things. The main noise source in the differential delay cell can be eliminated at the differential output, thus reducing phase noise. Implemented in an old TSMC 0.18 µm CMOS process, the Ring-VCO achieves a tuning range of 343.56-974.56 MHz. The phase noise at 1 MHz offset varies from -116.28 to -108.74 dBc/Hz, and the current consumed is 2.27 mA.

This paper proposes a novel sense-amplifier-based flip-flop (SAFF) applied in low-power, high-speed operation. With the employment of the pre-charge control technique and shut-off transistor, the power and delay of the proposed SAFF are significantly reduced. Furthermore, the proposed SAFF can provide low-voltage operation. Post-layout simulation results based on the SMIC 55 nm CMOS process show that the proposed SAFF achieves a 28.9% reduction in the CLK-to-Q delay and a 53.2% decrease in power (25% input data switching activity) and the power-delay-product of the proposed SAFF shows 3.0× improvement compared with the conventional SAFF.

This paper presents a lowpass filter for 5.8 GHz Doppler radar with an intermediate frequency signal hold function, which significantly reduces system power by interrupt mode operation. Additionally, it proposes a novel complementary push-pull DC offset calibration method to calibrate the DC voltage of the lowpass filter with the common mode voltage. Compared to traditional methods, the proposed scheme effectively stabilize the quiescent operating point of the receiver. The experimental results show that the power consumption of the proposed filter is 0.019 mW, calibrated DC voltage is 1.65 V, and residual DC voltage is less than 1 mV.

This paper proposes a multicell-to-multicell (MC2MC) equalizer based on the half-bridge bipolar-resonant LC converter (HBBRLCC), which collects energy from the consecutive more-charged cells (high-voltage group) through the positive and negative polarity selection switch matrix and the half-bridge switch matrix, and then releases the energy to the consecutive less-charged cells (low-voltage group). The paper includes configuration of the proposed equalizer, the mathematical model and simulation comparison with conventional equalizers, highlighting the superior high-speed balancing performance and excellent balancing efficiency of the proposed equalizer. An experimental prototype is built with four cells to verify the performance, and the balancing efficiencies in different balancing modes range from 81.45% to 87.62% with an average balancing power of 1.454 W to 5.011 W.

To improve the operational performance of Permanent Magnet Synchronous Motors (PMSM), a new voltage optimization algorithm is proposed. This algorithm is based on Particle Swarm Optimization (PSO) and incorporates two improvements: online optimization and secondary optimization. The improved PSO (IPSO) algorithm is applied to Dual-Vector Model Predictive Control (DVMPCC) for simulation and experimental research. The results show that, compared to DVMPCC, with similar speed response, the current ripple is reduced by 16.22% and the steady-state speed fluctuation is reduced by 65.14%. This indicates that the proposed algorithm is feasible and effectively improves the operational performance of the system.

In this letter, a 30MHz-3GHz 10W single pole double throw (SPDT) switch with 3.3V low supply voltage fabricated in 0.5um GaAs pHEMT technology process is presented. A feedforward capacitor pair is introduced in each stacked FET, which makes full use of the advantages of high breakdown voltage (V_BDG) of GaAs process under low supply voltage and enhances the power handling of each FET unit. Under specific power level, switch with reduced number of stacked FETs and low insertion loss are achieved. Meanwhile, uniform-partial-voltage stacked FET units with different gate width is applied to the switch design, which solves the problem of non-uniform partial voltage caused by parasitic capacitance(C_pd) between stacked FETs. As a result, the power handling of the switch is higher than 40dBm under continuous wave. Besides, the switch designed in this letter achieves 0.5dB insertion loss at 1.5GHz and the input and output return loss is less than -18dB at the whole frequency band. The test results verify the accuracy of the theoretical analysis.

The novel rare earth variable flux permanent magnet synchronous motor (PMSM) for electric vehicles is proposed. The structure and magnetic field regulation characteristics are analyzed, the variation of magnetic density, no-load back electromagnetic force and output torque with speed was studied through finite element simulation. The weak magnetic field expansion speed performance of the novel PMSM has been verified through experimental equipment. The adjustable electromagnetic field with running speed on the rare earth PMSM increases the high-speed operation range of vehicle.

A new sliding mode speed controller (NSMC) based on an improved genetic algorithm (IGA) is proposed to solve the problems of disturbance rejection and response speed differences in traditional vector control of permanent magnet synchronous motor (PMSM) driver systems. The improved algorithm adopts an adaptive crossover and mutation probability formula, which enhances the global search ability of the genetic algorithm. The algorithm is used to optimize the parameters of the sliding mode speed controller. Moreover, the sliding mode disturbance observer is used to generate feedforward signals to compensate for the influence of external disturbances. It is applied to the speed control loop to effectively improve the system’s robustness. Finally, numerical simulation results demonstrate the robustness and fast response of the proposed method.

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.

A wideband dual-line polarized antenna with low-profile property is presented in this paper. The dual-polarized antenna consists of two crossed antenna elements over a metal reflector and is excited by RF connectors vertically. Here, the crossed antenna element is based on Vivaldi radiator to obtain wideband performance. By loading resistors on the patches of Vivaldi radiator, not only the impedance matching of the proposed antenna can be improved further but also the profile is reduced greatly. Whatever, the loaded resistors can also depress radiation efficiency of the antenna element to a certain extent, especially in the lower band. For this reason, three periodic slots etched on the Vivaldi radiator are introduced herein to enhance the gain performance. To verify the feasibility of the proposed design, a prototype has been fabricated and measured. The results show good performance of a relative bandwidth of 153% for VSWR ≤ 2 (2-15 GHz) and a low profile of 0.22 λ_L (in terms of the lowest frequency of the band). Besides, the prototype can achieve an average gain of approximately 5 dBi and a maximum radiation efficiency of 80% within passband.

This letter presents a high-linearity single-pole five-throw switch implemented in a 0.13-μm silicon-on-insulator (SOI) CMOS process. In order to improve the linearity of switch, the uniform voltage division across the stacked-FETs is obtained by the proposed structure, which employs a resistive biasing network as well as compensation technology of drain-to-source capacitance and DC balance resistor. The measured input 0.1 dB compression point of the proposed switch is 42 dBm. Insertion losses are 0.38 dB and 0.5 dB for TX and RX modes at 0.9 GHz. The switch exhibits a second harmonic of -91 dBc, and third harmonic power of -84 dBc with a +28 dBm input power at 0.9 GHz.

Level-increased nearest level modulation (NLM) has been widely used in the modular multilevel converter (MMC) due to its simple implementation and low switching frequency in recent years. However, there are some disadvantages such as the poor performance of output voltage distortion and harmonic circulating current. A harmonic circulating current (CC) suppression method based on level-increased NLM is proposed in this paper. The impact of level-increased NLM on the CC is firstly analyzed. Then, a 5-voltage-level compensation method for harmonic CC suppression is proposed. Simulation and experiment verify the effectiveness of the proposed method.

In medical field, gaining access to blood vessels vitally important since it is the first step of many medical procedures. However, if vascular access is not established correctly, it causes complications. In this letter, we propose an algorithm that precisely segments blood vessels and automatically determines an injection point for injection robot systems using a monocular near-infrared vision system. The algorithm includes a Gaussian mixture model to determine the appropriate injection point for segmented blood vessels in a vision system and an ultrasound imaging system to estimate the depth of the blood vessel. Finally, we show the success rate of the proposed algorithm using phantom vessels.

An integrated sensor for temperature (Temp) and humidity (RH) measurement is designed. The temperature and humidity (T/H) sensing probe are combined with one first-order discrete-time Σ-∆ analog-to-digital converter (ADC). Also, a new ample architecture of ADC is proposed, ADC selects a reasonable reference voltage according to varied range of T/H signals. Therefore, the dynamic range utilization rate of ADC is improved. The proposed sensor is designed and fabricated in 0.153μm CMOS technology. The experimental results show that the T/H sensor achieves a −0.9∼0.6% RH measurement accuracy in the humidity range of 10∼90% RH, and ±0.4℃ temperature measurement accuracy in the temperature range of −40∼120℃.

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( f_T). Broadband operation is achieved using an enhanced degenerated Darlington f_T-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional f_T-doubler structures, the enhanced cascode Darlington f_T-doubler structure reduces the “V_CE mismatch” between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher V_CE for amplifying transistors, which represents higher f_T,_peak performance. Benefiting from the proposed Darlington f_T-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181- f_T bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than -35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

This paper presents a fully passive 2nd-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) designed specifically for low-power and low-cost Internet of Things (IoT) applications. By optimizing the coefficients, a substantial 24 dB in-band quantization noise suppression is achieved. To further reduce power consumption and the total unit capacitor count, a hybrid switching procedure and optimal logic are utilized. The measurement result shows that this design achieves an effective number of 10.31 bits over a 3.125 MHz signal bandwidth. At a power supply of 1.8 V, the power consumption is measured to be 728 µW with a sampling rate of 50 MS/s. Fabricated in 180-nm CMOS technology, the ADC core occupies an area of 0.117 mm². The Schrier figure-of-merit (FoM) of 160.13 dB is obtained.

Aiming at the problems of high complexity and large calculation quantity in the existing digital control strategies for single-inductor dual-output (SIDO) converter, this paper proposes a simple and reliable digital compensation control technology to suppress the cross-regulation. The design of the compensation control is only related to the selected circuit topology, thus it will not be redesigned for different control strategies. Taking the digital predictive current-mode (DPC) controlled SIDO buck converter as an example, the small signal model is firstly established. Based on these transfer functions, the theory of the proposed digital compensation method, which can suppress cross-regulation is analyzed. In the meanwhile, the digital control algorithm is derived. Simulation and experimental results verify the correctness of the theoretical analysis.

To improve the dynamic response performance and robustness of a permanent magnet linear synchronous motor (PMLSM)-based servo system, an adaptive proportional-integral-derivative (PID) controller based on a particle swarm optimization neural network is proposed. First, according to the mechanical dynamics equation of the PMLSM, a mathematical model of the PMLSM was established. Second, an adaptive PID speed controller is designed to realize real-time control of the PMLSM. To improve the dynamic performance and stability of the controller, a particle swarm optimization neural network is used to dynamically tune the parameters. Finally, the effectiveness of the proposed controller was verified on the MATLAB/Simulink simulation platform. Compared to the traditional PID controller, the adaptive PID controller can improve the dynamic performance of the system more effectively.

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

A novel buck-boost power converter is proposed to improve the performance of switched reluctance generator (SRG) system in an electric vehicle. In the proposed topology, the energy conversion part is formed by a buck-boost circuit and additional switches, with which, it is flexible to significantly boost the magnetization voltage and demagnetization voltage, thereby the output power range is improved and the power losses are reduced. The basic structure of the proposed converter is presented first and the attached operating modes are analyzed. The control strategy of the SRG system is then made to control the output voltage and the boost capacitor voltage. The simulation results show that compared to the conventional buck-boost converter, the proposed converter enhances the efficiency and reduces the power losses.

How to replace the referee in sports with artificial intelligence has attacked a huge amount of attention recently. In this paper, non-battery pressure detection and communication system are designed and fabricated aiming to help the referee in the basketball games. To get the information from player and ball at the same time, the designed system is consisted of three parts, including the basketball monitoring system, the shoes monitoring system, and the laptop to collect and process the data. For the basketball monitoring system, eight piezoelectric polyvinylidene fluoride (PVDF) flexible thin films are used as the sensor on the surface of the basketball with the sensitivity of 0.065 V/N and four hard piezoelectric Lead Zirconium titanite (PZT) patches are set inside the ball as the power source. As for the shoes monitoring system, four PZT patches work as both power source and pressure sensor with a sensitivity of 0.025 V/N. To solve the referee problem in basketball game, time delay of different systems is first measured. The different systems have similar time delay of about 3s, which will help to make sure whether the players break the rules. In this paper, whether the player has a traveling violation in a game can be refereed by the collected data, which has more than 97% accuracy. This work shows an innovative progress in automatic referees in games and the Internet of Things (IoT) in the human health monitoring.

Approximate computing has excellent result in error-tolerant applications sacrificing computational accuracy for better performance in the area, speed, and power consumption. As the most basic operation, addition is used in a large number of applications in various occasions. Therefore it is of great importance to optimize the performance of addition computation. In this paper, a segemented carry prediction adder (SCPA) structure is proposed, which splits the long carry chain into several short chains for parallel computation. The design parameters are diversified by adjusting the size of the blocks and the prediction depth of each subadditive to achieve different levels of performance. Flexible parameter tuning allows different design goals to be achieved based on specific performance requirements, which makes SCPA a useful design guideline for approximate adders. The error performance of SCPA is mesured by MRED, NMRED, ER, and other indicators and significantly has the best statiscal performace compared to similar designs. The proposed design is synthesized under TSMC 65nm process, and the result shows that the SCPA has a very nice accuracy-power tradeoff under 8-bit and 16-bit condition.

Transient execution attack does not affect the state of processor microarchitecture, which breaks the traditional definition of correct execution. It not only brings great challenges to the industrial product security, but also opens up a new research direction for the academic community. This paper proposes a defense mechanism for SMT processors against launching transient execution attacks using shared cache. The main structure includes two parts, a security shadow label and a transient execution cache. In the face of the side channel attacks widely used by transient execution attack, our defense mechanism adds a security shadow label to the memory request from the thread with high security requirement, so that the shared cache can distinguish the cache requests from different security level threads. At the same time, based on the record of security shadow label, the transient execution cache is used to preserve the historical data, so as to realize the repair of the cache state and prevent the modification of the cache state by misspeculated path from being exploited by attackers. Finally, the cache state is successfully guaranteed to be invisible to any attacker’s cache operations. This design only needs one operation similar to the normal memory access, thus reducing the memory access pressure. Compared with the existing defense schemes, our scheme can effectively prevent Spectre attack, and the overhead of performance is only 3.9%.