Traditional LLC converters suffer from efficiency degradation and load-dependent voltage regulation when operating off-resonance for wide output ranges. This paper proposes a dual-mode secondary-side modulated LLC topology. The primary side switches between Dual Full-Bridge (DFB) and Dual Half-Bridge (DHB) modes, significantly widening the output voltage range. Simple secondary-side PWM modulation achieves load-independent regulation and maintains ZVS operation at the resonant frequency for high efficiency. A PI-BPNN smooth transition strategy is introduced to mitigate voltage overshoot during mode switching. A 195 V input, 48.75-390 V output prototype validates the converter's advantages and the control strategy's effectiveness.

A practical copper-tape-based impedance matching circuit for helical antennas is presented, utilizing a Klopfenstein taper. The design uses standard acrylic cylinders and adhesive copper tape for low-cost fabrication without complex internal structures. The antenna achieves S₁₁ < -10dB from 3.8 to 6.4GHz, covering the 5.65-5.85GHz range, with stable reflection coefficient characteristics. The insertion loss of the matching section was experimentally evaluated using a two-antenna method based on the Friis transmission equation, and was found to be less than 0.15dB per matching section in the target operating band. This approach demonstrates a reproducible and low-loss matching technique suitable for microwave axial-mode helical antennas.

A compact monopole antenna designed for triple-band functionality in multiple application networks is proposed. This antenna simply contains a pair of antisymmetric L-shaped branches and is constructed on FR4 substrate, which occupies only a miniature volume of 10×20×1.6 mm³. By properly designing the branches based on multiple harmonic resonance, three impedance bands including 2.35-2.7, 3.3-3.7, 5.05-9 GHz can be completed with this antenna. The antenna's resonant characteristics can be easily adjusted by changing the lengths and widths of its branches. With a compacted size and suitable radiation performance, the suggested monopole antenna may well work as an internal antenna for LTE/Wlan/Wimax/5G NR/V2X/WiFi 7 band wireless applications.

This study proposes a topology optimization approach to reduce current imbalance in a power module with multi parallel-connected devices. In this study, the conductor layout is derived by a density-based topology optimization that minimizes the coefficient of variation (CV) of the device currents under constraints for grayscale suppression, open/short-circuit prevention, and preservation of the total current. In the optimized results with 12 parallel devices, several disconnections occurred when open/short circuit prevention and the binarization term were not applied. By incorporating both methods, the optimized layout maintained proper connection and reduced current imbalance.

Finite field inversion is a fundamental operation in cryptographic systems, particularly in Elliptic Curve Cryptography (ECC). The Itoh-Tsujii Algorithm (ITA) is a prevalent method for efficient inversion in hardware implementations within binary extension fields. This paper introduces an optimized parallel architecture for ITA that reduces computation time by minimizing clock cycles while maintaining a balanced trade-off in delay and area utilization. Our approach leverages a Hex-ITA framework in GF(2²³³), integrating Hex and Hex-root operations in parallel to enhance efficiency. The proposed design achieves a new benchmark in performance over existing designs. Experimental findings validate the scalability and performance of the proposed architecture, establishing it as a reliable choice for ECC-based cryptographic solutions.

Offset broadside coupled lines are widely used in directional couplers and quadrature hybrids. Ideally, these lines can achieve good isolation characteristics, but in the case of multi-section lines, the characteristics deteriorate due to the effect of junction discontinuities between lines. We propose a novel equivalent circuit model of junction discontinuities and a method for extracting equivalent circuit constants to understand this effect and design a compensating structure accurately. Using this proposed method, we modeled a multi-section quadrature hybrid coupler. We constructed a circuit model of the multi-section quadrature hybrid that agrees well with the results of full-wave electromagnetic(EM) simulations. This method enables simple and efficient structural design of complex circuit structures with multi-section coupled lines that require several hours or more for EM simulation.

This study applies a topology optimization approach to the design of a Junction Termination Extension (JTE), which is one of the edge-termination structures for vertical GaN power devices. Conventional parameter optimization requires independent tuning of the width, depth, and impurity concentration of the JTE region to achieve the desired breakdown voltage. As the number of target regions increases, the combinations of design parameters grow explosively. Consequently, severe constraints such as enforcing identical impurity concentrations across regions are often imposed, which substantially limit the design freedom. Focusing on the fact that a JTE structure can be represented as a dose distribution, we perform optimization with high design freedom using topology optimization. Since breakdown voltage correlates with the maximum electric field strength under reverse bias, we optimize the dose distribution to reduce the maximum electric field strength of the device. For a vertical GaN device biased at 900V in reverse, the proposed method reduces the maximum electric field strength by 12.5% compared with a structure obtained by parameter optimization.

This paper presents a high-resolution second-order delta-sigma (ΔΣ) ADC in 22nm FD-SOI technology. To overcome the trade-off between voltage headroom and linearity, a buffered dynamic body-Biased (BDBB) gate-bootstrapped switch is introduced. This structure decouples the input signal from the parasitic body capacitance, effectively suppressing harmonic distortion and minimizing aperture jitter. The modulator employs a cascaded integrator feed-forward (CIFF) architecture with gain-boosted op-amps, achieving a peak signal-to-noise and distortion ratio (SNDR) of 104.9 dB and an effective number of bits (ENOB) of 17.1 bits in a 10kHz bandwidth. A digital decimation filter performs 640× downsampling to provide a 24-bit output. Operating at a 1.2 V supply and 12.8 MS/s sampling rate, the proposed design achieves an spurious-free dynamic range (SFDR) of over 100 dB, making it highly suitable for high-precision signal acquisition.

In this letter, a 38 GHz asymmetric Doherty power amplifier (PA) that utilizes common-source (CS) amplifiers with different gate widths for the main and auxiliary PAs to align their optimal load impedances. Both the input quadrature hybrid network (QHN), output power combiner and inter stage matching network are designed by transformer-based structure. Furthermore, a quarter-wavelength impedance inverter is integrated into the output power combiner using a π-type C-L-C network, resulting in a more compact topology. The proposed Doherty PA, implemented in 65-nm CMOS process with a compact core area of 0.6×0.42 mm². At 38 GHz, the measured saturated output power (P_sat), 1-dB output compression point (OP1dB) and peak power added efficiency (PAE) are 19.7 dBm, 19.2 dBm and 25.4 %, respectively. The measured PAE at 6-dB power back-off (PBO) is 19.1 %.

In Systems-on-Chips (SoCs), logic locking is a vital technique for protecting Intellectual Property (IP) cores from leakage. Existing logic locking schemes based on Homomorphic Encryption (HE) employ a serial-blocking architecture, embedding high-latency cryptographic modules into the processor’s data path. This approach incurs significant performance overhead and limits the achievable security level. To address this bottleneck, this paper presents Homomorphic Feedback Locking (HFL), an architecture that decouples HE operations from the CPU’s execution path into a parallel, non-blocking feedback loop accessed via Control and Status Registers. We implemented HFL in a RISC-V SoC, characterized the privilege escalation event intervals under a system call workload, and developed a queuing model to analyze its performance overhead. Experimental results show that HFL with 83-bit security incurs a System Call performance overhead of only 15.0%, an improvement over the 33.5% overhead of a 41-bit serial-blocking scheme. Our model predicts performance scaling, explaining the overhead as a function of cryptographic workload and event arrival rate.

In this letter, a 0.2-20 GHz ultra-wideband low-noise amplifier is proposed and fabricated using a 0.15-μm E-mode GaAs pHEMT process. To achieve high performance across ultra-wide bandwidths, we innovatively propose a design methodology that systematically integrates parasitic parameters as core design variables. Based on the methodology, a negative feedback topology along with an ultra-wideband decoupling network is designed and have been implemented. The fabricated chip exhibits a gain of 15.6 dB across the 0.2-20 GHz range with a gain ripple of ±0.6 dB and a noise figure below 1.86 dB. S₁₁ and S₂₂ are better than -12 dB and -8 dB, respectively. The proposed LNA also achieves an OP_1dB of 17 dBm and an IP_1dB of 1.4 dBm under a power consumption of 400 mW. Additionally, the fabricated LNA occupies a chip area of only 1.5 × 1.0 mm², including all pads.

This paper proposes a bandgap reference (BGR) voltage source with high power supply rejection ratio (PSRR), low temperature coefficient (TC), and high robustness for automotive chip electronic systems. To reduce the temperature coefficient and save chip area, a self-biased high-order temperature compensation technology is developed in the design. The proposed BGR is implemented based on 180 nm process, with an effective area of only 0.01 mm². Experimental results show that under a supply voltage of 3.3 V, it outputs a reference voltage of 1.2 V, with an average temperature coefficient as low as 2.2 ppm/℃, a PSRR of up to −120 dB at the DC operating point, and a process coefficient of variation (σ/μ) of only 0.06%, which can meet the application requirements of automotive chips for high - precision reference sources.

Compared with single-edge designs, dual-edge-triggered flip-flops (DETFFs) can maintain the same data throughput while operating at half the clock frequency. However, when integrating ferroelectric nonvolatile structures with selector-based DETFFs, the uncertain logic levels of the clock and data signals during the restore phase may lead to unintended ferroelectric field-effect transistor(FeFET) programming. In addition, conventional C-element-based flip-flops suffer from limited performance. To address these issues, this paper presents an input C-element design that enforces input isolation by generating complementary outputs during the restore process, along with an improved output C-element. Experimental results show that, compared with existing C-element-based flip-flops, The proposed design reduces operating power by at least 33.3%, and decreases hold time by at least 58.8%. In addition, the clock-to-Q delay is reduced by at least 9.2%. The proposed flip-flop is capable of storing its output state prior to power-off and effectively isolating both data and clock signals during restoration, enabling accurate recovery of the pre-shutdown state while improving C-element performance.

This brief presents an ultra-low voltage (ULV) charge pump (CP) topology with high power conversion efficiency (PCE) designed for ultra-low supply voltage, low-power on-chip applications. The proposed ULV-CP employs a combination of dynamic gate-bias (DGB) and forward body-bias (FBB) techniques with the objective of enhancing overdrive voltage and reducing conduction losses, thereby enabling operation at ultra-low voltage. A 4-stage ULV-CP has been designed and implemented in a 22-nm FD-SOI process. Measurement result shows that it can reach a peak PCE of 83.87% at a supply voltage of 0.36 V. Compared to other CP circuits, the proposed circuit outperforms in terms of PCE, maximum output power, and minimum supply voltage.

In this letter, an optimal switching pattern-based asymmetric three-phase decoupled modulation strategy for six-phase inverter-fed dual three-phase PMSM drive is proposed to improve the steady-state performance, as well as maintain a low switching frequency. Therein, the equivalent voltage vectors for the decoupled voltage vectors in harmonic plane are established. An optimal switching pattern for asymmetric three-phase modulation strategy considering current harmonic suppression is proposed. Comparative studies are conducted to demonstrate the effectiveness of the proposed modulation strategy.

Data-retention flip-flop (DRFF) efficiently maintains data during sleep mode and retains state during transitions between active and sleep mode. This paper proposes a novel source-biased stacked inverter (SBS-Inverter) and a low-leakage, structure-reused DRFF. The sleep latch circuit constructed using the SBS-Inverter can effectively reduce the power of DRFF when storing data. Reuse of the structure improves the situation of redundant transistors in certain DRFF. Fine-grained inverter level optimization reduces delay and power during the active mode. The DRFF was implemented using a 55 nm process and subjected to comprehensive analysis. Post-layout simulation results at a supply voltage of 0.4 V indicate that the proposed DRFF’s data retention leakage power is only 5.3 pW. At a supply voltage of 0.8 V, the power-delay product is only 0.146 nW*ns@20 MHz. Monte Carlo simulation results considering process, voltage and temperature (PVT) variations show that the proposed DRFF can operate reliably down to a supply voltage of 0.4 V.

Power consumption is a critical challenge in integrated circuit (IC) design. Since post-synthesis power simulation is time-consuming, fast and accurate pre-synthesis power estimation, especially at the register-transfer level (RTL) stage, is essential for guiding power optimization. However, existing RTL-stage power models struggle to simultaneously achieve cross-design generality and time-based resolution, and often rely on large-scale labeled training datasets. We present AtomPower, a general machine-learning (ML)-based power modeling framework for per-cycle power estimation across diverse RTL designs. AtomPower introduces the register structure tree (RST) to decompose a circuit into a fine-grained, bit-level structural representation, enabling accurate time-based power modeling. To address multicollinearity in regression and derive reliable power labels, we develop a finite greedy clustering (FGC) algorithm that specializes conventional clustering methods by incorporating structural constraints. In addition, we propose a tailored data augmentation strategy to significantly reduce the reliance on large labeled datasets during training. Evaluated on a diverse set of designs, AtomPower achieves a Mean Absolute Percentage Error (MAPE) of 5.02% and a correlation coefficient (R) of 0.85, outperforming state-of-the-art RTL-stage power models in both estimation accuracy and data efficiency.

This paper proposes an external frequency synchronization control circuit for DC-DC converters, in which the frequency synchronization pin (SYNC) is shared with the enable pin (EN),enhancing chip compactness and reducing cost. The chip's enable state is not affected by the external clock signal. An internal phase-locked loop (PLL) ensures the continuity of the switching frequency variation, thereby avoiding output voltage overshoot caused by abrupt frequency changes. The chip supports a frequency synchronization ranging from 200 kHz to 2.4 MHz and is implemented using SK hynix's 0.18 μm BCD process. Test results show that the maximum output voltage overshoot is 58 mV with a 1 A load current and 1 MHz synchronization.

This work presents HiTAN, a hierarchical reverse modeling framework for automated analog IC sizing. Unlike conventional forward modeling, HiTAN directly infers design parameters from target performance specifications through an automated simulation-preprocessing pipeline combined with a lightweight multi-task attention mechanism. Validation on two representative LDO topologies demonstrates that HiTAN achieves high prediction accuracy, with an average parameter error below 2% and overall performance prediction accuracy exceeding 97%. Compared with baseline models, HiTAN consistently reduces design errors by a significant margin and generates parameter sets that satisfy multi-dimensional performance constraints, thereby enhancing circuit stability, efficiency, and robustness. These results confirm that reverse modeling not only accelerates the analog design process by reducing simulation overhead but also improves design quality and scalability for complex analog IC tasks.

In non-laboratory settings, high-precision detection of methane gas is vulnerable to noise and environmental interference. To address this issue, we propose a methane detection system that utilizes tunable semiconductor laser absorption spectroscopy technology combined with second harmonic detection. This system employs a hardware-algorithm collaborative design architecture to effectively suppress noise. In comparison to commercial non-dispersive infrared sensors, the detection limit of our system is reduced to 4.81 ppm, demonstrating enhanced long-term stability. The Allan variance is measured at 4.38×10^-7 over a duration of 147 seconds. Experimental results indicate that the system exhibits good response linearity within the range of 0-1000 ppm, with a coefficient of determination (R²) of 0.9818. This research offers a reliable solution for industrial methane monitoring, and the portable design concept may serve as a valuable reference for the development of other gas sensing systems.

A compact fundamental 140 GHz mixer using our in-house 80 nm T-gate InP HEMT process is designed, fabricated and characterized. A compact resistive topology is designed to enable low power consumption, high conversion gain and high integration. Measurement results show a maximum conversion gain of -9 dB and an IF bandwidth of 15 GHz within the 130 GHz-150 GHz range under a LO power of -1 dBm. The proposed resistive mixer features a compact size of 0.63 mm × 0.9 mm and can be fabricated with InP HEMT LNA on the same wafer. The results demonstrate that the mixer is well suited for integrated terahertz receiver front-ends.

This paper presents an 8-bit, 2-GS/s, time-interleaved analog-to-digital converter (TI-ADC) for communication systems. Featuring self-calibrating dynamic comparators in the sub-SAR ADCs to minimize offset and improve overall linearity. It breaks through the limitation that the offset calibration of traditional comparators tends to introduce quiescent power consumption. A circuit and layout for the TI-ADC have been designed in 40nm CMOS. Operating at a 1-V supply voltage and 2-GHz clock frequency with a Nyquist frequency input, the design achieves a SNDR improvement from 42.11dB to 47.11dB, and a SFDR improvement from 60.46dB to 63.64dB. The power consumption is 25.79mW.

The interconnection harness undertakes the critical task of power and signal transmission between in-vehicle electronic devices, and its electromagnetic compatibility (EMC) constrains the safety of vehicle systems. As the number of in-vehicle electronic devices increases and wiring becomes increasingly complex, the electromagnetic interference (EMI) issue between cables has become more prominent. Multiconductor transmission line (MTL) models suffer from limited computational efficiency when applied to the electromagnetic analysis of complex automotive wire harnesses. Although the equivalent cable bundle method (ECBM) offers an effective means of model reduction, it is commonly developed under the assumption of an ideal infinite conducting ground plane, which restricts its applicability in realistic vehicular environments characterized by finite metallic boundaries. To overcome this limitation, this paper presents an enhanced electromagnetic modeling approach within the ECBM framework, in which the effects of orthogonal finite metallic boundaries are explicitly incorporated into the per-unit-length parameter extraction. The proposed method is therefore well suited for automotive electromagnetic environments dominated by a limited number of nearby metallic structures. Simulation results demonstrate that compared with the MTL model, the proposed method can accurately predict crosstalk responses and radiation characteristics, with the simulation efficiency improved by approximately 50%. This method provides a new solution for vehicle EMC design and analysis.

The efficient physical memory allocation is essential for high performance, particularly in architectures that support translation look-aside buffer (TLB) coalescing. The binary buddy system (BBS) is a widely used page allocator that operates in the block level. However, it enforces rigid power-of-2 block size constraints. This constraint undesirably incurs memory fragmentation and can degrade the memory system performance. To resolve this issue, we propose an architecture-specific allocator, namely a page-table level aware buddy system (LBS). Considering modern embedded system on a chip (SoC), where input/output (I/O) devices run high-bandwidth 2D data applications, we present the algorithm, an analysis, and performance experiments. The experiments indicate that, by integrating TLB coalescing, LBS can significantly reduce fragmentation and improve memory system performance.

Photoacoustic imaging is a hybrid imaging modality that combines optical and ultrasound imaging, achieving the high contrast of optical imaging together with the high resolution of ultrasound imaging. Although commercial preclinical devices for photoacoustic imaging are available, they often suffer from a limited angle of view. In this paper, we present a three-dimensional (3D) photoacoustic imaging system employing a hemispherical ultrasound probe to overcome this limitation. Using the proposed system, we demonstrate the visualization of carotid thrombosis in a mouse model.

This paper presents a multi-step interpolation structure Time-to-Digital Converter (TDC) with a wide dynamic range, high resolution, and a robust anti-PVT mechanism. The architecture is based on a coarse counter, a middle-step interpolator implemented by a PLL, and a fine-step interpolator consisting of a multi-quadrant 2-D Vernier array. The coarse counter extends the TDC's measurement range, while the middle-step interpolator, as a key component of the PVT calibration module, significantly reduces nonlinearities caused by process, voltage, and temperature (PVT) variations. The proposed multi-quadrant 2-D Vernier array doubles the measurement range of the fine-step interpolator, while maintaining the TDC's resolution. The TDC was implemented in 180nm standard CMOS technology, with a reference clock frequency of just 10MHz, achieving a detection range exceeding 25µs and a fine resolution of 5.36 ps. To further compare the nonlinearities of the proposed multi-quadrant 2-D Vernier array with the traditional 2-D Vernier wide range comparator array, an existing theoretical model is used to analyze the DNL and INL, and both of them exhibit significant advantages and an optimization of over 50% can be theoretically achieved.

This letter presents a design strategy for a three-coupled transformer based _gm-boosting structure, which optimizes low noise amplifier (LNA) performance with rapid iteration design of the three-coupled transformer. The proposed strategy is used in a wideband LNA for phased array receivers operating at X-band. The three-coupled transformer based _gm-boosting structure is employed for gain and noise figure (NF) improvement, wideband input matching and a single-ended-to-differential conversion. Two CS stages are cascaded to provide higher gain and the inter-stage matching is implemented by two staggered transformers which extend the bandwidth (BW). The LNA achieves a measured gain of 21.5 dB and the −3-dB BW covers 7 to 14 GHz. The return loss is better than 10 dB across the BW. The measured NF is 3.0 dB at 7.5 GHz and the input third-order intercept points (IIP3) is −4.6 dBm at 14 GHz. The LNA occupies a core area of 0.21 mm² implemented in 40-nm CMOS process.

With the increasing demand for energy-efficient chips, various low-power flip-flops have been developed. Among these, TCFF has attracted significant attention for its ability to achieve low power consumption while maintaining overall performance. However, under advanced process technologies, TCFF faces challenges such as increased delay and potential functional failures caused by device aging. This paper proposes an anti-aging strategy for TCFF to address these challenges, leveraging the synergistic optimization of structural modification and Transistor size adjustment. Results demonstrate that TCFF exhibits reduced delay degradation across all corners. In particular, under the FF corner, the delay degradation of the rising and falling edges is mitigated by 19% and 12%, respectively. Moreover, the power-delay product (PDP) of TCFF increases by only 3.7%, while its static power consumption shows a slight reduction.

The wireless power transfer (WPT) system is widely used for its convenience. However, how to address the problem of misalignment is a hard problem to solve. This paper proposes a design method for an output-parallel Series-Series (SS) WPT system based on a designed splitting coil coupler. The method aims to optimize the parameters of coil structure based on the multi-island genetic algorithm. Besides, by designing splitting coils and specific parameters, the performance of misalignment tolerance of multi-channel coils is improved, and the detailed analysis is proposed as well. Finally, A 3.3kW splitting coil WPT system prototype is built. Compared to the traditional design, the proposed design can achieve a higher coupling with the same misalignment distance, as well as less power loss by the designed splitting coils.

High-speed Field-Programmable Gate Array (FPGA) packet-processing typically relies on streaming buses such as AXI-Stream for their explicit packet semantics, but high-speed I/O blocks including 200-400 Gbps Ethernet MACs and PCIe IP cores expose segmented buses that deliver multiple fixed-width segments per cycle. This mismatch motivates the need for efficient streaming-segmented bus conversion. This letter presents a structured FPGA architecture for bidirectional conversion between streaming and segmented buses, and demonstrates a prototype on AXIS and Intel Segmented Client Interface. The design integrates a high-speed dual-buffer organization with a metadata-driven mechanism that extracts frame-boundary and sideband information early in the pipeline. By decoupling control signals from payload, the proposed architecture shortens the critical path of the extraction Finite State Machine (FSM), thereby achieving high-frequency performance. The prototype implementation on an Intel Agilex 7 FPGA achieves 400 Gbps throughput at 415 MHz on a 1024-bit bus for packets of 128 bytes and above, with less than 3% resource usage. The architecture is parameterizable and can be mapped to other streaming and segmented bus formats with minor interface adaptation.

This paper proposes a disturbance-observer-based tuning-free controller (TFC) for magnetic-geared motors (MGM). To address the difficulty of conventional active damping controllers (ADC) in suppressing the flexible elements of magnetic gears and load inertia disturbances in MGM applications, a disturbance observer is introduced to enhance robustness. A detailed parameter design procedure is provided in the discrete domain, and theoretical analysis compares the suppression performance of the conventional ADC and the proposed TFC. Finally, experiments on the MGM prototype platform demonstrate that the proposed TFC exhibits stronger robustness against load inertia disturbances.

This letter presents a novel five-order Ka-band bandpass filter based on micro electromechanical system (MEMS) technology. The basic structure using air-filled with internal coupled lines and fully enclosed metal cavity has advantages of low dielectric and radiation loss, compact size, which is conductive to the design of high-frequency passive components. The resonant unit consists of metal cavity and parallel arranged open and short-circuited metal cores. Detailed design method is given to guide the Ka-band filter design. Moreover, it demonstrates the successful application of classical microstrip filter synthesis theory to the design of a complex 3D cavity-based MEMS filter. To enable easy integration with RF systems, a standard 50-Ω interface with ground-signal-ground (GSG) transition is added to the designed filter. Finally, the filter is fabricated and measured, and good agreements between the simulated and measured results are achieved.

This letter introduces a design methodology for a broadband high-efficiency power amplifier (PA) that incorporates a new symmetrical triangular low-pass filter with Embedded Radial Stub. To extend the design space, a resistive-reactive series of continuous inverse modes (Res.-Rea. SCIMs) theory is employed. The proposed filter, which serves as the output matching network of the PA, is constructed with dual-triangular symmetric (DTS) microstrip lines and a radial stub, which are interconnected by microstrip lines. By combining a DTS filter and a radial stub, a new filter with improved performance has been proposed. The new filter achieves low passband loss, high out-of-band rejection, and narrow transition bandwidth. These characteristics are well utilized in the inverse Class-F power amplifier, resulting in excellent performance. It is applied to the output matching circuit to realize a broadband high-efficiency PA. To validate the effectiveness of the proposed structure, a PA prototype is designed and fabricated with a 10-W GaN HEMT device. Measurement results demonstrate a bandwidth from 0.6 GHz to 1.4 GHz, with a drain efficiency (DE) of 66.3%-73.3%, a gain of 9.53-12.17 dB, and an output power of 39.53-42. 17 dBm.

This paper presents a novel ergodic sequential logic (ESL) neuron model capable of mimicking typical excitabilities of biological neurons and realizing excitability suitable for artificial neural networks. Utilizing this model, a novel ESL spiking neural network is presented and its learning mechanism is also designed based on the actor-critic reinforcement learning framework. It is demonstrated that the presented network can enable an agent to solve a navigation task by providing appropriate actions. Additionally, comparisons indicate that the presented ESL spiking neural network is significantly more hardware-efficient than a traditional spiking neural network. Finally, potential applications for the ESL spiking neural network are discussed.

This paper presents a background current suppression strategy based on a redundant segmented digital-to-analog converter (RS DAC). The utilised DAC employs thermometer coding for the lower segment and binary coding for the higher segment, incorporating redundancy at the segment interface to enhance robustness against mismatch. To benchmark our approach, we conducted a Monte Carlo analysis. The results demonstrate that our suppression scheme achieves an order-of-magnitude improvement in mismatch tolerance. Additionally, A dedicated calibration algorithm was developed specifically for the RS DAC. To validate the proposed strategy, a capacitor trans-impedance amplifier (CTIA) chip was designed based TSMC 180nm process. The measurement results confirm that the background current suppression strategy effectively reduces background current, offering a practical solution for detectors experiencing high background levels.

A vector-processor architecture based on the RISC-V extended instruction set is proposed and evaluated for the acceleration of post-quantum cryptographic(PQC) algorithms. The core employs an in-order, partially four-way multi-issue pipeline and delivers a significant speed-up over pure-software RISC-V implementations. Unlike previous hardware–software co-designs that target specific PQC schemes, the instruction-set extensions are derived from fine-grained, fixed-point arithmetic primitives; consequently, the same core can speed up current NIST candidates and tolerate future algorithm updates while remaining useful for other cryptographic workloads. The processor was implemented in 28nm SMIC HKE+ process, and post-layout simulations were conducted. Results showed that under primary PQC standards, compared with the state-of-the-art counterparts, it can achieve a reduction in total cycles by 9.1%-12.7%. In terms of stream cipher, block cipher, and hash cipher algorithms, it can achieve 12×-24× performance improvement, which enables it to have higher flexibility in practical application scenarios.

This work presents a 32 Gb/s tunable equalizer implemented in 65 nm CMOS. The design combines an active inductor CTLE with NCC and a source-follower buffer, overcoming the gain-bandwidth trade-off of traditional CTLEs while maintaining stable behavior under PVT variations with a DC gain variation of 5.6 dB. A 2-tap full-rate DFE further suppresses residual ISI. The results show that the proposed equalizer compensates for a 29 dB channel loss at the 16 GHz Nyquist frequency. It achieves an eye opening of 204 mV vertically and 0.77 UI horizontally at 32 Gb/s NRZ. The post-layout area is only 0.0015 mm². Furthermore, with a power consumption of only 4.6 mW, the equalizer achieves an exceptional energy efficiency of 0.14 pJ/bit.

This letter proposes a high-linearity bootstrapped switch designed for application in SAR ADC. The proposed switch introduces an auxiliary capacitor branch to the conventional bootstrapped switch. By connecting other branches on the bootstrap signal channel to the auxiliary capacitor branch, the capacitor parasitic effect on the bootstrap signal channel is diminished, thereby reducing the overall parasitic capacitance of the circuit and improving both the linearity of the sampling switch and its response speed to signals. Simulation verification based on a 55nm CMOS process library demonstrates that at a sampling frequency of 10 MHz, the proposed structure achieves an Signal-to-Noise-and-Distortion Ratio (SNDR) of 89.86 dB, and an Spurious-Free Dynamic Range (SFDR) of 94.52 dBc.

Accurate modeling of self-heating effect in power transistors is crucial for reliable design and performance evaluation of wireless communication circuits and systems. This letter presents an enhanced time delay neural network (TDNN) technique specifically developed to model power transistors considering self-heating effect. At first, an enhanced TDNN model topology suitable for power transistors is proposed. To accurately describe the self-heating effect, a thermal sub-circuit is incorporated into the model framework. Moreover, novel formulations for direct current, small-signal S-parameters, and large-signal harmonic balance outputs of the proposed TDNN are derived so that typical measurement data can be utilized for model training. Finally, training algorithm is also proposed to effectively optimize the weighting and thermal parameters in the proposed TDNN model. The effectiveness of the proposed technique is validated through a modeling example involving a practical power transistor. The resulting TDNN model is embedded in Keysight Advanced Design System, and simulation results based on this model demonstrate good agreement with the measured data.

For wireless power transfer systems, constant current (CC) output, constant voltage (CV) output, and zero phase angle (ZPA) switching are critical research priorities. This paper proposes an LCC-LCC/S hybrid compensated converter integrated with an auxiliary switch-controlled capacitor (SCC). By adjusting the parameters of the SCC, the LCC-LCC compensation topology can achieve load-independent CC output at a fixed frequency under ZPA conditions. Similarly, the LCC-S compensation topology enables load-independent CV output under the same operating conditions. Experimental validation is conducted on a 19.42 kHz prototype, which stably delivers 2 A and 60 V with a peak efficiency of 90.7%.

This paper analyzes the generation mechanism of input harmonics and the inherent contradiction between bandwidth expansion and efficiency degradation in extended continuous mode. It theoretically demonstrates the necessity of implementing input harmonic control and proposes a joint input-output harmonic control technique to compensate for the efficiency sacrificed in extended continuous mode to increase bandwidth, thereby better balancing the efficiency and bandwidth performance of the power amplifier. A 1.6-2.8 GHz high-efficiency broadband extended hybrid continuous power amplifier is designed to verify this theory, with a saturation efficiency of more than 66% and a saturation power of more than 39.8dBm.

This paper presents a Synchronized Switch Harvesting on Capacitor and Inductor (SSHCI) circuit designed for piezoelectric energy harvesting, which combines the SSHI method with the SSHC operation. Initially, the proposed SSHCI circuit employs synchronized switches to perform the SSHC operation, allowing for energy harvesting from the Piezoelectric Transducer (PZT). Following this, it transitions into the SSHI operation to invert the charges on the PZT, thereby enhancing the working voltage. Additionally, the traditional diode rectifier bridge found in conventional circuits is removed by the voltage doubling rectifier circuit to decrease the power loss. An experimental platform has been developed to evaluate the power generation performance of the proposed circuit. The results indicate that the SSHCI circuit achieves a peak power output that is 9.8% greater than that of the existing parallel SSHI circuit and 13.2% greater than that of the serial SSHI circuit, respectively.

This paper proposes a BJT-based frequency-domain temperature sensor of a voltage-to-frequency converter (VFC) and error compensation. The key design is that the two base-emitter voltages from the detection front end are converted by VFC into corresponding frequency signals. To achieve high accuracy, an error compensation method calibrates errors arising from the VFC loop delay and comparator offset. Implemented in a 0.18μm SMIC process, the sensor achieves an error of -0.35°C∼+0.75°C throughout a temperature range of the -40°C∼125°C. The sensor has an average conversion time of 3.5ms, a power consumption of 270μW, and an area of just 0.065mm².

To reduce transmission loss in printed wiring boards (PWBs), materials with low dielectric loss tangent, such as oligo(2,6-dimethyl-1,4-phenylene ether)-based resins, are commonly used. In this study, we fabricated PWBs blending poly(2,6-dimethyl-1,4-phenylene sulfide)-based resins (PMPS-V), in which benzene rings are connected via sulfide rather than ether bonds, and evaluated its effects. The PWBs exhibited a low loss tangent of 0.0017 and achieved UL94 V-0 flame retardancy with only one-third the conventional flame retardant content. Transmission loss and eye diagram degradation up to 30 GHz were effectively suppressed after heat testing at 150 °C. It was clarified that PMPS-V contributes to improving the thermal reliability of PWBs.

A 12-bit pipelined successive approximation register (SAR) analog-to-digital converter (ADC) is proposed, which operates at a sampling rate of 800-MS/s. With the assist of cross-coupled inverter pair, a gain-enhanced high-linearity open-loop residual amplifier (RA) based on gm-ratio achieves a high power efficiency and speed with complete steady-state and dynamic performance characteristics. The process, supply voltage, and temperature (PVT)-sensitive gain of RA is compensated by the adjustable bias current in the cross-coupled inverter pair. The prototype single channel ADC is integrated in an 8-channel time-interleaved ADC and implemented in a 28-nm CMOS process, which consumes 5.52 mW at 1-V supply voltage and 800-MS/s sampling rate. The measured inter-stage gain variation remains below 2% across a temperature range of -20-80 °C, achieving an SNDR and SFDR of 60.1 dB and 72.4 dB, respectively. The Walden figure of merit (FoM) is 8.35 fJ/conversion-step, and the Schreier FoM is 168.7 dB.

This paper presents a high gain DC-DC converter based on multiple coupled switching inductors. The converter adopts a structure with three switching inductor units connected in series with a switching capacitor unit. Due to the conduction characteristics of the diodes, the primary sides of the three coupled inductors alternately operate in parallel and series states with the switching actions of the transistor. Furthermore, the proposed converter utilizes only a single switch, which simplifies the control strategy of the converter. Finally, in order to verify the conclusions obtained from the theoretical analysis, a prototype with an input voltage of 25V, an output voltage of 362V, and a rated power of 120W is constructed.

This paper proposes a low-offset balanced inverter that forms a push-pull structure using two composite transistors. Each composite transistor operates as either a current-sourcing or a current-sinking device, and can replace both the PMOS and NMOS transistors in a CMOS inverter. The symmetry between the pull-up and pull-down paths achieves a very low offset, enabling the implementation of a single-ended, lossless integrator without requiring any offset cancellation. The proposed balanced inverter is applied to realize a second-order delta-sigma ADC that digitizes the integration of extremely weak input currents from the resistor. Experimental results from the fabricated chip demonstrate that the resistor measuring ADC achieved a 0.4-Ω resolution over 106-dB dynamic range, confirming its practical applicability despite the process and temperature variations.

Multi-view stereo (MVS) 3D reconstruction is a fundamental task in computer vision, aiming to recover accurate scene geometry from multi-view images. However, existing methods continue to confront formidable challenges when handling complex scenes. To effectively address the above issues, this paper introduces an improved multi-view stereo-matching framework, AC-GoMVS. To mitigate the susceptibility of standard convolutions to depth noise at occlusion boundaries, we introduce an Adaptive Geometry-aware 3D Convolution (Agp-Conv3D) that exploits a dual-stream architecture comprising a principal pathway and a residual pathway. Furthermore, a dynamic attention mechanism is incorporated into the main path to adaptively adjust sampling positions of depth hypotheses, significantly improving edge detail reconstruction. In addition, a channel attention mechanism is embedded within the geometry consistency aggregation module to dynamically recalibrate the weight distribution of multi-level geometric features, addressing the feature mismatch issue caused by fixed-weight kernels in traditional 3D convolutions. Simultaneously, skip connections and residual links interlaced between the downsampling and upsampling pathways not only preserve rich fine-grained information, but also markedly enhance feature diversity. We evaluated our method on the DTU dataset and the Tanks and Temples benchmark. Experimental results show that, compared with the baseline model, the proposed approach achieves better reconstruction quality and stronger generalization ability.

The variation of oscillator amplitude in inductive position sensors causes a change of noise level on receiving coils, restricting the feasibility of off-line calibration. A method of piece-wise-linear amplitude regulation, realized by adjusting a 7-bit control word n<6:0>, is proposed for oscillators with a wide-range tail current. The n<6:0> is divided into 6 segments, and tail current is made to change exponentially with n<6:0> from segment to segment. This ensures a constant relative amplitude step across all segments, enabling both fast and accurate amplitude regulation. An oscillator with tail current ranged from 0.168 mA to 10.4 mA was designed in a 0.18 μm CMOS process. Simulation results show the maximum amplitude variation at all segments is no more than 70 mV and settling time is the duration of n<6:0>’s monotonic transition from its initial to its final value, in which the affection of amplitude variation upon position accuracy is negligible.

Capacitive power transfer (CPT) do not produce eddy current effects and are concentrated between plates. To increase the capacitance of CPT coupler and satisfy the charging demands of loads, a novel coupler and its associated compensation network are proposed. The coupler elevate the equivalent capacitance to nanofarad-scale. The compensation network designed in this paper can achieve input zero phase angle (ZPA) and load-independent constant-voltage (CV) output. Experimental results demonstrate that the designed coupler's equivalent capacitance is several times greater than that of traditional structures. The compensation network successfully meets the requirements for input ZPA, CV output, and anti-misalignment performance.