IEEJ Journal of Industry Applications
Online ISSN : 2187-1108
Print ISSN : 2187-1094
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3 巻 , 4 号
選択された号の論文の13件中1~13を表示しています
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Special Issue on “Power Electronics”
Special Issue Paper
  • Toshiji Kato, Kaoru Inoue, Kyu Takano, Kazunari Yamada, Ariyasu Aki
    3 巻 (2014) 4 号 p. 288-295
    公開日: 2014/07/01
    ジャーナル フリー
    This paper presents an efficient pulse-width modulation (PWM) method to optimally reduce switching (SW) losses in three-phase neutral-point clamped (NPC) inverters in one switching cycle using a new two-phase modulation scheme. The proposed method digitally selects an optimum switching vector (SV) pattern, which minimizes an estimation function based on switching losses considering phase currents among possible reduction patterns for one switching cycle. The proposed modulation method is further extended to reduce common-mode voltages in three-phase NPC inverters. The basic principle involves elimination of the common-mode voltage by limiting the combinations of the output phase voltage levels of the three-level NPC inverter. A modified space vector generation technique based on the two-phase modulation method is proposed to reduce both common-mode voltages and switching losses. The proposed PWM method was experimentally verified for output voltages of the NPC inverter connected to a universal load. The method reduced the number of switching transitions for the largest or second largest current, and it can automatically adapt to different load conditions. The method was also experimentally validated for its EMC and switching loss reduction capability.
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  • Aromhack Saysanasongkham, Masayuki Arai, Satoshi Fukumoto, Shun Takeuc ...
    3 巻 (2014) 4 号 p. 296-303
    公開日: 2014/07/01
    ジャーナル フリー
    A sampling algorithm to immunize digital control power converters with triangular carrier waveforms against switching noise is introduced. Many converter circuits employ a sawtooth carrier waveform; however, no optimal sampling method has been presented that avoids switching noise. As demonstrated by the experiments conducted in this research, there are cases where converter circuits are not correctly controlled and sample values are affected by switching noise via current sensors or AD converters. As a result, the output is unstable and inaccurate thus reducing the reliability of the converter.  This paper proposes an adaptive sampling method for a digital control current-mode power converter circuit on an FPGA (Field Programmable Gate Array) with the PWM (Pulse Width Modulator) sawtooth carrier waveform. To avoid noise overshoot and undershoot during the MOSFET's switching process, the sampling timing of the AD converter is adaptively tuned according to the duty ratio of each switching cycle. We further introduce a random phase noise generator, to conduct simulations as realistic as practical experiments. We also present simulation and experimental results of the proposed methodology illustrating cases of successful noise avoidance. Thus, we verify that the proposed sampling method improves the reliability of power converter circuits.
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