A method for fabricating electroplated structures using side wall electrical contact has been developed. This method consists of three key processes: first, a lift-off process using an aluminum sacrifice layer; second, an electroplating process using side wall electrical contact between the aluminum sacrifice layer and the metal layer; and third, a conductive layer removal process, which prevents abnormal etching due to a local cell effect of the metal layers. In the lift-off process, a roof shaped pattern is fabricated by side-etching an aluminum layer. It is easy to remove the metal layer and the resist. In the electroplating process, the resistance of the electrical contact in the side-wall between the aluminum sacrifice layer and the metal layer is nearly equal to that of a conventional seed layer and can be applied as a feed line. In the conductive layer removal process, the aluminum sacrifice layer is an amphoteric, and can be removed with a dilute alkali solution. With this method, abnormal etching of the electroplated structure and the metal layer does not occur.

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This paper presents a long bar type silicon resonator with a high quality (Q) factor and an evaluation of the hermetic packaged device. This research aims at developing the integration technology of the capacitive silicon resonator on LSI for application of a timing device. The structure of the silicon resonator is defined by deep reactive ion etching of the top Si layer of a silicon on insulator wafer, and then the patterned top Si layer is transferred onto a low temperature co-fired ceramic substrate. Fabricated resonator is hermetically sealed by anodic bonding technique. The resonator is excited in the extensional bulk acoustic mode at a resonant frequency of 9.69 MHz. The Q factor measured for this device is approximately 368,000 at vacuum chamber pressure of 0.01 Pa. Additionally, the dependence of the Q factor on the operating pressure is measured in order to evaluate the vacuum level of the hermetically packaged device.

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The stress-life characteristics of two groups of single-crystal silicon fatigue-test specimens were measured with each group having different etched sidewall surfaces. Specimens with vertical surface roughness exhibited S-N relationships with larger scattering shifted to the bottom-left side which indicates a shorter lifetime and lower strength. The experimental results were compared with stress distribution analyses and were explained adequately by the degree of stress concentration around the notch tip, which was caused by a reduction of the curve radius due to an additional small structure. Comparisons between the test results and crack growth propagation analyses suggested that direct adoption of roughness height as an initial crack was an inappropriate way to estimate the effects of roughness.

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We propose a new approach to synthesize a carbon nanotube (CNT) - copper (Cu) composite on a silicon substrate using combination of supercritical fluid deposition (SCFD) and electrochemical plating (ECP) process. The measured density of the composite is 8.2±0.3 g/cm³, and the volume percentage of voids is 3∼6%. The evaluated thermal resistance including the thermal interface resistance and bulk resistance of the composite is 28.4∼42.1 mm²KW^-1. It shows the potential ability of the CNTs-Cu composite for thermal interface material.

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