In advanced technology nodes, transistors and interconnects with shrinking physical dimensions suffer large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the effect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation/aging modeling to circuit-level analysis. In addition, active techniques to counter these effects, such as clock skew tuning and voltage tuning are also covered in this paper.

A scan chain is used by scan-path test, one of design-for-test techniques, which can control and observe internal registers in an LSI chip. On the other hand, a scan-based side-channel attack is focused on which can restore secret information by exploiting the scan data obtained from a scan chain inside the crypto chip during cryptographic processing. In this paper, we propose a scan-based attack method against a hash generator circuit called HMAC-SHA-256. Our proposed method is composed of three steps; Firstly, we isolate 64 bit-transition groups from a scan data using scan signatures based on the property of the HMAC-SHA-256 algorithm. Secondly, we classify these 64 bit-transition groups into 32 pairs. Lastly, we find out the correspondence between the scan data and the internal registers in the target HMAC-SHA-256 circuit. Our proposed method restores the secret information by the three steps above, even if the scan chain includes registers other than the target hash generator circuit and hence it becomes too long. Experimental results show that our proposed method successfully restores two secret keys of the HMAC-SHA-256 circuit using up to 425 input messages in 7.5 hours.

Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design and verification today is to find new ways to increase the productivity. For software development the agile methodology as an incremental approach has been proposed and is heavily used. Behavior Driven Development (BDD) as an agile technique additionally enables a direct link to natural language based testing. In this article, we show how BDD can be extended to make it viable for hardware design. In addition, we present a two-fold strategy which allows to specify textual acceptance tests and textual formal properties. Finally, this strategy is complemented by methods to generalize tests to properties, and to enhance design understanding by presenting debug and witness scenarios in natural language.

High-level synthesis (HLS) significantly reduces hardware design time. Unfortunately, the users of HLS usually have to manually rewrite algorithm C code for satisfactory synthesis results. These manual tunings of C code often cause extra design time and decrease the advantage of HLS. One of such manual tunings is array access optimization. Large arrays are implemented as RAMs in HLS, so reducing array accesses in C code can increase performance of synthesized hardware since access conflicts to the RAMs are reduced. Furthermore, the removal of all accesses to arrays leads to the complete removal of the RAMs corresponding to the arrays. By successful application of scalar replacement to C code, data read from RAMs or written to RAMs are stored in shift registers, and these shift registers are accessed instead of the RAMs when reusing the accessed data, thus array accesses are completely removed. Unfortunately, the most advanced scalar replacement method for nested loops cannot appropriately handle array accesses with constant subscripts. This paper proposes a scalar replacement method to solve the problem. In particular, we target a subset of C code called Static Control Part (SCoP) for which we can build the mathematical representation called the polyhedral model. The proposed method builds elaborate reuse information tables with the polyhedral model. Differently from the previous method, the proposed method replaces each reuse destination that has multiple reuse vectors with scalar variables. These scalar variables are referenced conditionally according to the conditions in the reuse information tables. With the experimental results, we demonstrate that the proposed method decreases the area of synthesized hardware significantly and improves circuit performance compared to the most advanced scalar replacement method for nested loops in the case of C code which contain array accesses with constant subscripts.