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Displaying 1-17 of 17 articles from this issue
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Article type: Cover
Pages Cover1-
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (13K) -
Article type: Index
Pages Toc1-
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (59K) -
Kazuhide Nanba, Makoto Nagata, Takashi Morie, Atsushi IwataArticle type: Article
Session ID: IPU99-67
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA high-speed and low-power piplined analog-to-degital (AD) converter using folding technique is proposed. Comparing with existing folding AD converters, the proposed AD converter operates at a higher sampling frequency due to pipline operation and dissipates lower power due to small scale circuits thanks to selecting only necessary interpolation source signal. The AD converter was designed with 0.35um CMOS technologies. We have good outlook for realizing a 6bit AD converter which can operate with a power dissipation of about 120 mW at 200MS/s by circuit simulation.View full abstractDownload PDF (925K) -
H. Kodama, M. Nagata, T. Morie, A. IwataArticle type: Article
Session ID: IPU99-68
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThe conventional Δ Σ A/D converter has been used for audio application area. We proposed the high-speed Δ Σ A/D Converter using Voltage Controlled Oscillator (VCO) as a quantizer which could work at wide bandwidth and low power supply. To convert at video application area, we designed the 0.6μm CMOS test chip and obtained 48-dB (SNR) at 2.5-MHz bandwidth by experimental results, but the performance degraded by the harmonic distortion.View full abstractDownload PDF (988K) -
Akihiko Nogi, Ichiro Fujimori, Tetsuro SugimotoArticle type: Article
Session ID: IPU99-69
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESS24-bit digital-to-analog converter (DAC) that achieves 120dB A-weighted dynamic range and power dissipation of 320mW, has been developed for DVD audio. This paper describes two key design issues in this development. One is the multi-bit delta-sigma architecture optimized for highend performance, and the other is the power efficiency in analog design for low-noise and highlinearity. A multi-bit delta-sigma DAC architecture optimized for reduced clock jitter tolerance, chip area and power dissipation was presented.View full abstractDownload PDF (686K) -
Yuko Tamba, Kazuo YamakidoArticle type: Article
Session ID: IPU99-70
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA 6b 500MSample/s full-flash A/D converter (ADC) has been developed. To achieve high-speed performance, pre-amplifier and comparator DC coupling structure is adopted. And to reduce the offset voltages, per-comparator offset calibration circuits are used. Cascaded comparators with input reset switches and push-pull input stage improve the resolution. To achieve high accuracy for high frequency input, a track-and-hold (T/H) circuit is used. The power dissipation is minimized by using distributed hold capacitors structure. This ADC achieves 5.5 effective number of bits at a 125MHz analog input in 0.4μm CMOS.View full abstractDownload PDF (762K) -
Yuji GendaiArticle type: Article
Session ID: IPU99-71
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSPRML technology had applied to storage systems over ten years. Keeping pace with the experience, there are an amount of papers on it. However, there seem few comprehensive texts that clarify assumptions and constructions of the technology. This paper aims at the points. First, we explain Nyquist equalization in time domain and step forward to the idea of the "Partial Response." Assuming rational input/output waveforms, we can get a closed form expression of the ideal PR equalizer. Maximum Likelihood criteria, path metric and Veterbi algorithm are clearly distinguished. Finally, we refer to practical aspects such as equalizer circuit and clock recovery PLL.View full abstractDownload PDF (1035K) -
Takahiro Hanyu, Michitaka KameyamaArticle type: Article
Session ID: IPU99-72
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents a new asynchronous data-transfer scheme based on two-color two-rail complementary coding, which is suitable for a multiple-valued current-mode VLSI circuit. Two kinds of R-valued two-rail complementary signals, called ' two-color two-rail codes, ' which represent 'data values, ' are used in odd and even phases, respectively. The sum of R-valued two-rail complementary values in an odd phase is a constant (R-1), while the sum of R-valued two-rail complementary values in an even phase is also a constant 3 (R-1). The difference of these constant values in the two-color coding makes it easy to detect a data-arrival state from a data-transition state without spacers. Moreover, basic components to realize the above asynchronous VLSI system, a signal-state detector to detect a data-arrival state, and a two-color code generator to produce two-color two-rail signals can be easily designed by a multiple-valued current-mode circuit technology based on dual-rail differential logic. Finally, the advantage of the proposed asynchronous multiple-valued VLSI circuit is demonstrated in comparison with the corresponding binary implementation.View full abstractDownload PDF (730K) -
Masanori FURUTA, Shoji KAWAHITO, Yoshiaki TADOKORO, Hiroyuki OKADAArticle type: Article
Session ID: IPU99-73
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSCCD color image sensors are widely used for many applications. Signal processing such as white balancing for digital still/video cameras using CCD image sensors is usually performed in digital domain. However, because of the sensitivity deviation among R, G and B pixels, the SNR is limited by the low sensitivity pixel. This problem can be solved by processing the white balancing in analog domain. This paper proposes a new gain control amplifier (GCA) with white balancing. The proposed GCA with analog white balancing allows us to achieve higher SNR in the amplified image while maintaining sufficient gain precision of 10bit and low power dissipation. The power consumption is estimated to be 119mW at supply voltage of 3.3V and 20MHz pixel rate.View full abstractDownload PDF (577K) -
Koichi Miyanaga, Mamoru SasakiArticle type: Article
Session ID: IPU99-74
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThe recording density of modern hard-disk drives is high in order to provide low-cost data storage. As a result, adjacent bits are stored close together on the disk media and intersymbol interference (ISI) is severe. This paper presents a current-mode continuous-time transversal filter with the aim of equalization to a baseband communication digital channel like hard-disk drives. Delay blocks are main block for the transversal filter. We describe an analog delay circuit which is 3-pole lowpass filter and propose multiple phase lock loop (MPLL) locking the delay charactristic. The delay circuit consists of integrator, current mirror and OTA and it realizes5ns constant time delay on wide bandwidth (0〜50MHz) with 4.7mW power consumption. We disigned an integrator decreasing the influence of parasitic conductance and the integrator has high DC gain more than 60dB. The CMOS circuit is fabricated in 1.48μm CMOS process and it operates in 3V power supply.View full abstractDownload PDF (686K) -
Shinya Yamamoto, Mamoru SasakiArticle type: Article
Session ID: IPU99-75
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn discrete time analog signal processing, flowting CMOS analog switches (transmission gate) can't be utilized for low power supply voltage, because of the threshold voltages. In this paper we propose a 3-state (input, output, Hi-impedance) Current-Memory which make flowting analog switches unnecessary and make it possible the discrete-time analog signal processing with low power supply voltage. It uses only granded analog switch, and a common gate circuit to realize low input impedance. We apply it to A/D converter and Sampled-data filter by using Switched-Current (SI) technique. The performance of the proposed circuits are confirmed by Hspice Simulation.View full abstractDownload PDF (675K) -
Mamoru Sasaki, Shinya YamamotoArticle type: Article
Session ID: IPU99-76
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSCurrent mode circuits are receiving attention because of low power supply operation. The common-gate current mirror has improved in the performance without requiring high supply voltage. However, it has difficulty in being applied to high frequency filters due to parasitic poles. In this paper, it is presented that the transfer function of the common-gate current mirror can be approximated as second order low-pass function and the free frequency and the quality factor are controllable with the bias currents. In addition, we propose a design method for realizing a high order low-pass filter by cascading the common-gate current mirrors. As an example, 6 order phase linear low-pass filter with 50MHz cutoff frequency has been designed using 1.5μm CMOS process and 1.5V power supply. High performance (0.91mW power consumption, 0.31% THD (1MHz), 0.88% THD (50MHz), 0.6% group delay error) of the filter has been confirmed using HSPICE simulation.View full abstractDownload PDF (530K) -
Satoshi Sugino, Yasuko YamamotoArticle type: Article
Session ID: IPU99-77
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA feasibility study of a 3rd Order type-II CMOS frequency synthesizer circuit is made with circuit simulation analysis. A 0.3um CMOS (3metal-2poly) technology is selected for the present work. The required passive elements are also fully integrated in to the circuit. The phase noise and the stability analysis are made by a C like software. As well as each building blocks in the circuit, the whole circuit is verified by SPICE Simulator also. The results show that the circuit with the area of 0.7mm2, power dissapation of 40mW@3v, phase noise of -110dBc@1MHz is attainable for the paticular case.View full abstractDownload PDF (595K) -
Mitsuo Baba, Yasushi Aoki, Masaki Sato, Yasushi Wakayama, Hiroyuki Yas ...Article type: Article
Session ID: IPU99-78
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper describes a digital CDR (Clock Data Recovery) circuit for PON systems. Results of this CDR circuit have shown 0.4-U. I. p-p jitter and ±40% duty cycle distortion tolerance within 2-bit pull-in time. The circuit has been implemented on 3.3V, 0.35μm CMOS cell-based IC, and used for our PON systems of 50Mbps-156Mbps. In our evaluation, performance of this CDR with our O/E conversion circuit has met ITU-T G. 983 standard (FSAN specification).View full abstractDownload PDF (611K) -
Toshio Fujisawa, Jun Hasegawa, Taketoshi Tsujita, Yoshimitsu Shimojo, ...Article type: Article
Session ID: IPU99-79
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have developed a switch access LSI, SAM, which functions as an interface to an ATM switch fabric. It constitutes a 20Gbps switch system with another two chips. SAM has remarkable features that include UPC cell discarding, and shaping port. Additionally, SAM provides various ATM layer functions required in most ATM switch systems. In this paper, implementation of SAM, policing and shaping functions will be described, and then evaluated value will be shown. The accuracy of the policing function is less than 0.01%. The standard deviation of cells transmitted from the traffic shaper is less than 80ns.View full abstractDownload PDF (933K) -
Ichiro Hatakeyama, Takeshi Nagahori, Kazunori Miyoshi, Yasuaki Nukada, ...Article type: Article
Session ID: IPU99-80
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA 12-channel parallel optical receiver LSI has been developed for intra-and inter-cabinet interconnections in switchings systems, and routers with Tb/s-class throughput. The LSI was fabricated using 0.44-μm BiCMOS technology. It incorporates automatic decision threshold control circuits, which are optimized for receiving non-coded parallel optical data, and a power supply circuit to suppress inter-channel crosstalk in the chip. An optical dynamic range exceeding 10dB, a skew tolerance of 380 ps, and a power consumption of 1.35 W with a 3.3-V power supply were obtained at 1-Gb/s/ch operation. These results indicate the suitability of the receiver for intra-and inter-cabinet interconnections with Gbyte/s-class throughput.View full abstractDownload PDF (1019K) -
Article type: Appendix
Pages App1-
Published: September 21, 1999
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (82K)
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