ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
24.27
Showing 1-15 articles out of 15 articles from the selected issue
  • Type: Cover
    Pages Cover1-
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Type: Index
    Pages Toc1-
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Hirofumi Sumi, Kazuya Yonemoto, Ryoji Suzuki, Takahisa Ueno, Koichi Sh ...
    Type: Article
    Session ID: IPU2000-22/CE2000-1
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We developed a new APS(Active Pixel Sensor)CMOS image sensor to be used as the core device to input a imaging information. In this CMOS imager, HAD(Hole Accumulation Diode)technology and unique imaging circuits with CDS(Correlated Double Sampling)noise canceling function was incorporated. As a result, 1/3 inch 330k-pixel VGA format sensor could be fabricated, and good image reproduction was achieved with drastic reduction of FPN(Fixed Pattern Noises).
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  • Ikuko I., H. Nozaki, H. Yamashita, T. Yamaguchi, H. Ishiwata, H. Ihara ...
    Type: Article
    Session ID: IPU2000-23/CE2000-2
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We have developed a low voltage buried photodiode for CMOS imager, in order to achieve high quality reproduced images comparable to CCD imager. The new buried photodiode has been operated in complete charge transfer mode at low voltage of 3.3V, and the image lag and kTC noise of the photodiode have been suppressed.
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  • Yoshikazu Ino, Takayuki Hamamoto, Masami Akaik, Kiyoharu Aizawa
    Type: Article
    Session ID: IPU2000-24/CE2000-3
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We propose a new method of 8bit Analog to Digital Converter(ADC)on an image sensor using integration time information. 8bit ADC can be done by using small 1bit comparator which detects each bit during integration, repeatedly. We have designed a prototype by using column parallel architecture. The prototype has 32×16 pixels and 8bit memory for each pixel. We describe the processing scheme of our ADC and the circuit and layout design of the prototype. We show results of some experiments.
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  • K. Takada, Y. Tanaka, Y. Kusaka, S. Nakamura, S. Yano, T. Kakumoto, Y. ...
    Type: Article
    Session ID: IPU2000-26/CE2000-5
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    New three methods to cancel the non-uniformities of the output signals from each pixel of a CMOS Area Logarithmic-converting Image Sensor fabricated by using standard CMOS process have been developed. They utilize three types of reset-operation for the purpose. In the first type, a reference corrent source is used. In the second type, a constant-voltage is used. In the third type, a clock applied to the source of the MOSFET that converts the photocurrent to the voltage logarithmically proportional to the amount of incident light is used. In result the voltage offsets caused by the non-uniformities of the output signals from each pixel have reduced from about 20mV(rms)to 8.1mV, 1.49mV and 2.8mV(rms)by each method, respectively.
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  • Akihiro Uehara, Naoyuki Tokida, Takashi Tokuda, Jun Ohta, Masahiro Nun ...
    Type: Article
    Session ID: IPU2000-27/CE2000-6
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    We propose and demonstrate a vision chip that can detect eye-safe light by using SiGe heterobipolar transistor process. This process realizes monolithic integration with an eye-safe heterophototransistor(HPT)and CMOS circuits. The responsivity of the HPT is simulated and is found to have enough sensitivity in the eye-safe region. To employ the HPT in a vision chip, we design a test chip with pulse frequency modulation circuits, which has a wide dynamic range without accumulation action. The chip designed using 0.35μm CMOS 2P3M process works well under a power supply of 0.7V and has a dynamic range of 20dB and a power consumption of less than 1μ W. Also mutual inhibition is implemented in the chip to realize elemental image processing function.
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  • K. Sawada, S. Kawahito, K. Tada, Y. Tadokoro, M. Ishida
    Type: Article
    Session ID: IPU2000-28/CE2000-7
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    Highly sensitive and simplified infrared image sensors are proposed. A pyroelectric sensor was adopted as an infrared light sensing device of the image sensor, because the pyroelectric infrared light detector has the highest sensitivity in the thermal type detectors. However the output signal from the pyroelectric detector is only affected the variations of infrared light intensity, so a conventional pyroelectric type infrared image sensor needs light chopping system. Therefore it is difficult to develop simple and small infrared light camera using pyroelecric devices. In this paper, we found a possibility of a chopperless highly sensitive pyroelectric type infrared imager using a new sensing scheme. In this scheme, the image sensor chip is vibrated in one direction, and time differential and spatial integration functions are integrated on the image sensor chip.
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  • Kang-Wook Lee, Tomonori Nakamura, Katsuyuki Sakuma, Nobuaki Miyakawa, ...
    Type: Article
    Session ID: IPU2000-29/CE2000-8
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A new three-dimensional(3D)integration technology based on wafer bonding technique has been proposed for intelligent image sensor chip with 3D stacked structure. We have developed key technologies for such 3D integration. A 3D image sensor test chip was fabricated using this 3D integration technology. Basic electric characteristics were evaluated in the 3D image sensor test chip.
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  • [in Japanese], [in Japanese], [in Japanese], [in Japanese], [in Japane ...
    Type: Article
    Session ID: IPU2000-30/CE2000-9
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
  • Takayuki Kimura, Hiromitsu Shiraki
    Type: Article
    Session ID: IPU2000-31/CE2000-10
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    To improve the performance of the frame transfer scheme CCD image sensor, we proposed a new CCD shift register. The register consists of a series of buried photo diodes driven from isolated overflow drain through the barrier. The performance of the register was simulated by using three dimensional numerical analyses. It was clarified that low dark current, signal charge multiplication, and charge handling capability, that is several times greater than that in the conventional devices, were simultaneously achieved.
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  • Ichiro Itoi, Hiroaki Shibuya, Jaroslav Hynecek
    Type: Article
    Session ID: IPU2000-32/CE2000-11
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    This article describes the theory of operation and characterization results of a new charge detection amplifier, which detects charge that moves in the bulk of a silicon CCD channel. The charge detection is nondestructive and, therefore, kTC noise free. The new detector is suitable for a very high speed and a low noise operation needed in high-resolution CCD image sensors. A simple gradual channel transistor approximation is used to derive the first order device model which then predicts the charge conversion sensitivity, linearity, and noise. The derived theoretical results are compared with detail measurements that include the measurement of conversion gain, linearity, reset feed through, noise, and hot carrier effects. Finally, from the analysis and from the measurement results, it is concluded that the BCD(Bulk Charge Detection)concept is superior to today's state-of-the-art FD(Floating Diffusion)charge detection amplifiers in high-speed applications.
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  • M. Furumiya, K. Hatano, I Murakami, T. Kawasaki, C. Ogawa, Y. Nakashib ...
    Type: Article
    Session ID: IPU2000-33/CE2000-12
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    A 1/3-inch 1.3M pixel interline-transfer charge-coupled-device(IT-CCD)image sensor with a high-frame-rate skip mode has developed for digital camera applications. We have now developed and tested a high-frame-rate skip mode(75 frames/s)and an advanced 3:1 interlaced-scan mode. We developed a method of separately implanting boron ions for the vertical CCD and horizontal CCD in single-layer electrode CCDs with small pixels, to maintain a high charge-transfer efficiency. A new thin-flattened-layer microlens improved the sensitivity dependence on camera lens aperture. At an f number of 1.4, for example, there was an 18% increase in photo-sensitivity.
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  • Yong-Gwan Kim, Tetsuo Yamada, Hideki Wakoh, Tetsuo Toma, Tomohiro Saka ...
    Type: Article
    Session ID: IPU2000-34/CE2000-13
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
    Pixel interleaved array progressive scan CCD image sensor has been developed. The number of pixels is 2.3M(2480(H)x1860(V)/2)and It's effectively 4.6M when with pixel interpolation. This device has four Merits. The first is that progressive scan only with 2 layer poly-Si is realized. The second is wide dynamic range of 71dB by efficient pixel pattern layout. The third is high sensitivity of 340mV(5100°C IR cut, 1200nit, F5.6)by to gather photons through equilateral aperture. The 4th is high resolution of 1.4times high in H&V direction with pixel interleaved array.
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  • Type: Appendix
    Pages App1-
    Published: March 24, 2000
    Released: June 23, 2017
    CONFERENCE PROCEEDINGS FREE ACCESS
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