Substrate noise is quantitatively evaluated by gain calibrated substrate voltage measurements in a 100 ps-100 μV resolution. Activity in a digital block is a key amount to which the noise intensity is proportional, and its reduction is a straight and universal solution to suppress the noise. Use of Kelvin grounding in the source circuits and placing a guardband proximate to the receiver circuits together also attenuates the noise significantly, however, the effect is limited to the low frequency components such as a ringing.
Analyses of the substrate noise propagation in the silicon substrate, which are injected during switching operations of logic circuits, are necessary for high performance mixed analog-digital LSI circuits. An equivalent circuit of the CMOS logic noise source, and an F-matrix equivalent circuit model of the substrate with metallic ground wiring systems, are used for simulating the noise generation and propagation in a substrate noise evaluation test chip. Simulated and measured results are very consistent in waveform shapes, in attenuation effects by the propagation, and also in the peak noise amplitudes approximately within 15%.
This paper presents the architecture, circuit and layout design of a 200MS/s 8bit CMOS ADC with 3.0V supply voltage. The ADC employs the folding/interpolation architecture to reduce hardware, power and input capacitance while maintaining the high-speed operation. Current steering folding circuits combined with current mode interpolation are proposed which are suitable for high-speed low-voltage operation. SPICE simulations with BSIM3v3 parameters of MOSIS 0.35μm process shows the 200MS/s operation of the circuit with 300mW power. The chip is fabricated through MOSIS.
The recycling integrator correlator(RIC)is a novel approach for implementing correlators that consume less power than conventional digital or analog CMOS correlators. The RIC modulates the product of a received signal and a pseudorandom noise(PN)sequence into a bit stream by first order ΔΣ modulation. The accumulated number represents the quantized correlation value. Using RIC's, two functional blocks of a DS-CDMA demodulator targeting IMT-2000, a matched filter(MF)and a delay locked-loop(DLL), are implemented in silicon. Processed in a 0.35-μm double-metal double-poly CMOS process, the RIC-MF and the RIC-DLL respectively dissipate 23mW and 3.4mW at 2-V power supply.
A 1-GHz portable digital delay-locked loop(DLL)with infinite phase capture ranges has been developed. In order to achieve a low jitter digital DLL, we have developed a master-slave architecture that achieves infinite phase capture ranges and low latency, a delay line that improves the delay time resolution, a phase step suppression technique and a dynamic phase detector with increased sensitivity. Measured results showed that the DLL successfully achieves 29-ps peak-to-peak jitter with a quiet supply and 0.2-ps/mV supply sensitivity.
A 3.3-V, 156-Mbps laser diode(LD)driver with a mixed-signal feedback-type automatic optical power control(APC)has been devised for both a quick APC response of 1.5 μs and the long holding time of optical power level between burst-data packets of more than 10-s for optical burst-mode transmissions. The LD driver is fabricated in standard triple-well 0.35-μm CMOS technology, which can compensate for the degradation of LD optical power, moreover, any external adjustment of optical pulse width is unnecessary.
A radio frequency integrated circuit using Si is a key device to achieve a small, low-power, and low-cost mobile terminal. Until now, almost all of the RF-IC were integrated in a single chip. Furthermore, a direct-conversion transceiver, which can reduce external components such as filters, was developed. It will be very important to develop a low-loss passive component, a low phase noise VCO of high Q on-chip inductor, and a small loss package in the next decade. A bipolar transistor is still adopted to RF-IC mainly, however, SiGe will be adopted for high frequency and low power applications. The CMOS RF-IC will realize analog-digital mixed mode circuits such as radio LANs.
Reported here is a duty cycle repeater(DCR)which obtains 50% duty-cycle complementary clock signals from a wide range of input duty-cycle signals from 30% to 70%, even when input signals suffer from timing skew. It features a simple CMOS structure, with a newly developed complementary phase blending architecture and a symmetrical phase blending inverter.
For 40-Gb/s optical receivers, we developed a preamplifier with a high transimpedance gain of 791 Ω and a wide-bandwidth of 40.8 GHz by using 0.2-μm self-aligned SiGe HBT technology. To increase the bandwidth, commonbase input stage was introduced in front of conventional transimpedance amplifier. Furthermore, a Cherry-Hooper-type amplifier following the transimpedance amplifier increased the preamplifier gain.