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Displaying 1-15 of 15 articles from this issue
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Article type: Cover
Pages Cover1-
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (12K) -
Article type: Index
Pages Toc1-
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (64K) -
Yoshitaka MURASAKA, Makoto NAGATA, Youichi NISHIMORI, Takashi MORIE, A ...Article type: Article
Session ID: IPU2001-52
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe developed a substrate noise analysis methodology employs chip-level substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with the time-series divided parasitic capacitance model. The methodology enables rapid and reliable estimations of substrate noise waveforms. And substrate noise waveforms for 0.6μm CMOS 4.5mm square chip with practical digital circuits are simulated and compared with measurements with a 100ps - 100μV resolution. Peak to peak substrate noise amplitudes are roughly with the average error of 10% compared with measurements for conventional as well as reduced substrate noise designs.View full abstractDownload PDF (853K) -
Makoto Nagata, Takafumi Ohmoto, Yoshitaka Murasaka, Takashi Morie, Ats ...Article type: Article
Session ID: IPU2001-53
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSActivity controllable noise source and arrayed substrate voltage detectors use a 0.25-μm, 2.5-V CMOS technology and enable substrate noise measurements with controlled logic density/activity distributions. These circuits are used for exploring effects of power-supply parasitic components on substrate noise generation in practical large-scale CMOS digital circuits. Spatially distributed parasitic impedances on power-supply and return wirings cause the noise generation locally, and moreover, screen the effect of noise attenuation by parasitic capacitances of logic elements working as charge reservoirs.View full abstractDownload PDF (837K) -
Hidekuni Takao, Fumie Ina, Toshiaki Douzaka, Kazuaki Sawada, Makoto Is ...Article type: Article
Session ID: IPU2001-54
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, a precision SOI-CMOS amplifier for high temperature sensor interface circuit is presented. Autozero technique was used to realize precision analog signal processing over a wide temperature range. It is based on a novel two stage autozeroed operational amplifier designed to reduce clock feedthrough error. The offset drift due to the leakage current at high temperatures is compensated with a novel circuit configuration. In the fabricated circuit, the effect of charge injection was reduced to about 20% offset voltage in a typical autozeroed amplifier. Furthermore, input offset drift was suppressed within 1mV from RT to 200℃.View full abstractDownload PDF (951K) -
Masato NAKAKITA, Mamoru SASAKIArticle type: Article
Session ID: IPU2001-55
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSCurrent mode circuits are receiving attention as basic blocks for analog-digital mixed-signal circuit. It has been already reported that(1)introducing class AB operation to a current memory reduces noise and charge-injection[6]and(2)a current mirror with common-gate amplifier has wide-band second-order low-pass characteristic and cascading the mirrors realizes a high-oder low-pass filter[7]. Two ICs have been fabricated and evaluated their performance. One is an algorithmic A/D converter composed of the current memories with class AB operation. Another is a 6th-order low-pass Bessel filter implemented by cascading the current mirrors with common-gate amplifier. In this paper, the results of the fabrication and evaluation are reported.View full abstractDownload PDF (816K) -
Akira MATSUZAWAArticle type: Article
Session ID: IPU2001-56
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents an overview of design methodology both in the analog CMOS and in the mixed signal LSI. The important design considerations in analog CMOS are first discussed. Not only taking the conventional methodology into account but also taking care of the process fluctuation including V_T mismatch or 1/f noise lead to robust and high quality analog CMOS circuits. For the rapid-growing high frequency applications, parasitic effects such as cross-coupled capacitance and substrate power loss are becoming serious issues. Thus it is demonstrated that pre- and post-layout simulations are vital to achieve target characteristics. The mixed-mode simulation using SPICE, Verilog-D, and Verilog-A, which can concurrently handle analog and digital circuits, is shown to be essential to the overall mixed signal system design. The substrate noise or EMI need to be analyzed effectively nuder such environment as well. Finally accurate device parameter extraction, its careful reflection to above circuit designs, and fine parameter control in manufacturing for the active and passive devices are described.View full abstractDownload PDF (853K) -
Mamoru SASAKIArticle type: Article
Session ID: IPU2001-57
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSCurrent mode circuits are receiving attention as basic blocks for analog-digital mixed-signal circuit. It has been reported that a current mirror with common-gate amplifier has wide-band second-order low-pass characteristic and cascading the mirrors realizes a high-order low-pass filter. However, in order to apply it to waveform equalizer in read channel IC, some finite zeros realizing gain boost, must be introduced into the transfer function. In this paper, a method is proposed that introduce some finite zeros and make it possible to apply the high-order filter to waveform equalizer. In addition, the circuit is fully differentiated to get the noise immunity on mixed-signal environment. As an example, in order to implement an equalizer for 800Mb/s digital communication system, cutoff frequency 400MHz, 2nd order gain-boost, 8th order low-pass Bessel filter are designed using 0.35μm CMOS process. High performance(gain variation < 0.14dB, group-delay variation < 1.5%, THD(400MHz)< 0.5%, power consumption 45mW, active area 0.05mm^2)of the filter has been confirmed from HSPICE simulation.View full abstractDownload PDF (797K) -
Kazuyuki WADA, Yoshiaki TadokoroArticle type: Article
Session ID: IPU2001-58
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA scheme reducing error on source followers due to body effect is proposed. A node of a source follower which is fixed to a DC voltage source is excited by a control circuit so that an output signal is well compensated. The scheme employs an additional source follwer for detecting error of an original source follower. Since the error is algebraically analyzed, a characteristic of a control circuit for tuning the node potential is easily solved. Based on the scheme a level-shift circuit is given and its effectiveness is confirmed through computer simulations.View full abstractDownload PDF (724K) -
S. Miyatake, M. Miyamoto, K. Ishida, T. Morimoto, Y. Masaki, H. TanabeArticle type: Article
Session ID: IPU2001-59
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents a 320 x 240 pixel CMOS active pixel image sensor(APS)with a transversal readout architecture that eliminates the vertically striped fixed pattern noise(FPN). There are two kinds of FPNs for CMOS APSs. One originates from the pixel-to-pixel variation in source-follower threshold voltage, and the other is from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and a column-reset transistor, a source follower input transistor, and a column-select transistor instead of the row-select transistor in conventional CMOS APSs. The column-select transistor is connected to a signal line, which runs horizontally instead of vertically. Every horizontal signal line is merged into a single vertical signal line via a row-select transistor. The imager exhibits neither a vertical nor horizontal stripe FPN.View full abstractDownload PDF (925K) -
Jun OHTA, Takao HIRAI, Keiichiro KAGAWA, Masahiro NUNOSHITA, Masashi Y ...Article type: Article
Session ID: IPU2001-60
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have proposed an image sensor for detecting modulation light. A pixel circuit TEG has been fabricated using 0.35μm CMOS process. A photogate is used for the photodetector. We have experimentally confirmed the demodulation output for the modulated illumination of 5kHz under the background of 100μW/cm^2. It is found that the n-diff regions in the both side of the photogate acts as a pocket of charge and affects the demodulation performance.View full abstractDownload PDF (618K) -
Shoji KAWAHITO, Nobuhiro KAWAI, Yoshiaki TADOKOROArticle type: Article
Session ID: IPU2001-61
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn this paper, we propose a method of low-noise signal readout using frame oversampling and a CMOS image sensor with non-destructive high-speed readout mode. The technique enables the use of the high-gain column amplifier and the digital integration of signals without noise accumulation. The column amplifier is effective to reduce the noise due to the wideband amplifier and the quantization noises. Simulation results show that the noise can be reduced by a factor of 20log_<10>M[dB]where M is the oversampling ratio.View full abstractDownload PDF (552K) -
T. WAKAMATSU, N. INOKIHARA, T. HAMAMOTO, K. AIZAWAArticle type: Article
Session ID: IPU2001-62
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have been investigating a new technique of on-sensor analog to digital conversion. In this paper, we describe a new 64×32 pixels A/D conversion image sensor. In this sensor, small 1bit comparators detect each bit of pixel value by using non-destructive readout in column parallel, repeatedlly. We have fabricated the second prototype by 2-poly 2-metal 0.8μm CMOS process. We describe the processing scheme of our ADC, simulation results, and the circuits and layout design of the second prototype. We show results of some experiments obtained by the prototype.View full abstractDownload PDF (1233K) -
Toshihisa Watabe, Hiroshi Ohtake, Masahide Goto, Hideki Kokubun, Toshi ...Article type: Article
Session ID: IPU2001-63
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe developed a CMOS readout circuit with a high S/N for a solid-state HARP imaging devices. A CMOS readout circuit is composed of a charge transfer type voltage multiplier and CDS circuit. Signal charges produced in a pixel are transferred to a smaller capacitance by this charge transfer circuit and signal voltage can be amplified. This circuit is arranged in each column. A prototype chip was fabricated and the characteristics were evaluated. A measured data shows that the circuit can reduce vertical FPN by 4dB and random noise by 16dB compared with the line amp type readout circuit.View full abstractDownload PDF (613K) -
Article type: Appendix
Pages App1-
Published: September 06, 2001
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (75K)
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