ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
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25.61
Displaying 1-15 of 15 articles from this issue
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  • [title in Japanese]
    Article type: Cover
    Pages Cover1-
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_Cover1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Index
    Pages Toc1-
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_Toc1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • A Single-Chip MPEG2 HDTV Decoder LSI for DTV Recording/Playback Systems
    Yasuhiro Watanabe, Koji Yoshitomi, Hidenaga Takahashi, Yukio Otobe, Ki ...
    Article type: Article
    Session ID: CE2001-20
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_1
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We developed MPEG2 decoder LSI for DTV recording/playback systems.It integrated TS decoding, MPEG2 video decording, format conversion, 2D-graphics and other functions on a single chip. This LSI incorporates some stream processing functions and enables the smooth execution of trick plays without complex operations in an external CPU. It is suitable for the applications to a high-performance and lowcost DTV recording/playback systems.
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  • An Advanced Multimedia Processing LSI Suitable for HDTV Applications^<[1]>
    Hiroki Mizosoe, Kazuhiro Maeda, Hiroshi Sakurai, Hiroyasu Otsubo
    Article type: Article
    Session ID: CE2001-21
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_7
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We have newly developed a multimedia processing LSI, targeting HDTV applications such as a digital broadcasting receiver based on ATSC or ARIB stantaras. It integrates many essential features such as multiple HDTV/SDTV input and output ports, an MPEG2-I/JPEG decoder, programmable video scahing engines, alpha-blending and a 2-D graphic engine. The chip can also achieve a multi-image display function by combining the elementary functions discussed. This LSI will be very useful in a broad-range of multimedia applications such as DTV/ATV receivers, set top boxes, interactive TVs, cables and satellites.
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  • One-pass VBR MPEG Coding using Scene Adaptive Dynamic GOP Structure
    Akio Yoneyama, Hiromasa Yanagihara, Yasuyuki Nakajima
    Article type: Article
    Session ID: CE2001-22
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_13
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In this paper, we propose an algorithm for one-pass VBR(Variable Bit Rate) MPEG video encoding. We use two techniques to enhance the picture quality in the one-pass VBR coding. One is scene adaptive dynamic GOP(Group of picture) structure control technique according to the picture characteristics estimated by macroblock(MB) activity information. The other is precise bit budget prediction technique for appropriate bit allocation using the activity and motion characteristics analysis. Since the processing speed of the proposed algorithm is almost equal to that of the conventional MPEG CBR encoder without GOP control, fast VBR encoding can be realized with better picture quality than that of fixed GOP structure.
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  • A Transport Stream Processing LSI for HDD Recording and Playback of HDTV
    Hiroyuki Nagata, Masahiro Yamada, Noriya Sakamoto
    Article type: Article
    Session ID: CE2001-23
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_19
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In the next generation digital TV receivers, a recording capability is one of the most attractive features. We have developed a new digital TV recording system utilizing a hard disk drive(HDD). We also developed a new LSI that contains IDE controller and transport stream processor with a dedicated RISC processor. This system records and playbacks the transport streams based on the MPEG2 System Layer. Since the new LSI supports most of the recording and playing-back process, the host CPU power can be used for other applications such like GUI applications. In this paper, system architecture and a bitrate contol algorithm are described.
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  • DVD Recorder : Development of the Second Generation of DVD Video Recorder system
    Hidetaka Kurusumi, Hirofumi Ide, Takeshi Umeda
    Article type: Article
    Session ID: CE2001-24
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_25
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We have developed the Second Generation DVD Video Recorder "DMR-E20" with the 4.7GB DVD-RAM Drive, that can read and write on the DVD-R discs. Main characteristics of "DMR-E20" are as follows: - Simultaneous Recording and Playback for DVD-RAM - Hybrid VBR Recording for DVD-R discs - Seamless Playback We report about the hardware system, software structure, and the control method that materialized the new function of the "DMR-E20".
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  • Development of low-power LSI for portable MD player
    Shinetsu Kato, Isao Kato, Tetsushi Kasahara, Tetsuhiko Kaneaki, Kazuhi ...
    Article type: Article
    Session ID: CE2001-25
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_31
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    New generation Signal-Processing-and-Servo-Control LSI for portable MiniDisc player has been developed. Very low power consumption was achieved by introducing the technologies, such asJitter-Free reproduction method, Intelligent commands, Optimizing circuit architecture, and newly developed digital signal processing circuits. The LSI is applied to the portable MD player SJ-MJ88, which has been put on market from Nov.2000. The player is capable of playing back 110 consecutive hours with one rechargeable battery (NiH, 1400mAh) and one alkaline battery(Type-C).
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  • A 79dB-SNR 70mW 18MHz CCD front-end with fully-digital amplification scheme
    Shozo Nitta, Kenji Tanaka
    Article type: Article
    Session ID: CE2001-26
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_37
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    This paper presents a fully monolithic 10bit front-end for CCD cameras which incorporates a 14bit Analog-to-Digital Converter(ADC), a Digital Programmable Gain Amplifer(DPGA) and an Optical Black(0B) clamp loop. With the adoption of fully-digital ampliication scheme, it solves almost all the problems associated with the conventional front-ends and attains low-noise, low-power robust gain characteristic. Test results show 79dB SNR(@Gain=0dB) with the power consumption of 70mW@18MHz.
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  • DIGITAL CAMERA FOR TAKING EVIDENTIAL PHOTOGRAPHIC IMAGES
    H. Morito, K. Anzai, D. Watanabe, H. Yoshiura, Y. Seto
    Article type: Article
    Session ID: CE2001-27
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_43
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    A picture taken by a digital camera cannot be used as evidence in a court of law because it is hard to detet modifications made after the picture was taken. This paper describes a system for making evidential digital photographic images by using digital signatures and digital watermarks. It also describes a prototype digital camera demonstrating the feasiblity of the system.
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  • Dynamic range compression based on illumination compensation
    Masami Ogata, Takashi Tsuchiya, Takeshi Kubozono, Kazuhiko Ueda
    Article type: Article
    Session ID: CE2001-28
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_49
    CONFERENCE PROCEEDINGS FREE ACCESS
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    This paper presents a new approach for effectively compressing the dynamic range of a visual scene while preserving the local contrast in order to reproduce a high quality image on devices with limited dynamic range. In this method, dynamic range compression is performed through a reduction of the illumination effect, by taking into account the characteristics of the human visual system. To precisely extract the illumination component with a reasonable complexity, amulti-scale nonlinear filtering scheme was developed. The effctiveness of the proposed method is demonstrated by using natural images captured by double exposure technique.
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  • THE SEMANTIC SCORE METHOD : A TOOL FOR QUANTITATIVE CONTENT EVALUATION BY MULTIPLE VIEWERS
    Yasushi Takahashi, Yoshiaki Shibata, Mikio Kamada, Hitoshi Kimura
    Article type: Article
    Session ID: CE2001-29
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_55
    CONFERENCE PROCEEDINGS FREE ACCESS
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    This report proposes (1)the Semantic Score method for deriving an integrated score that represents a group of semantic scores obtained from multiple viewers, and (2)an algorithm that generates a video clip using the semantic scores, for the purpose of automatically generating a video clip that reflects the cognitive evaluation of narrative content by viewers. This makes it possible to semi-automatically produce various video clips according to viewer characteristics based on the semantic scores of a large number of viewers collected at movie and TV drama previews. It also makes it possible to intuitively select program titles or browse content from moving images using meta-data based on semantic scores in a storage-based broadcasting environment.
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  • A proposal for Internet connectivity and interconnectivity of home appliances based on a remote display framework
    Tomohiro Haraikawa, Tadashi Sakanoto, Tomohiro Hase, Tadanori Mizuno, ...
    Article type: Article
    Session ID: CE2001-30
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_61
    CONFERENCE PROCEEDINGS FREE ACCESS
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    This paper proposes a network extension of home appliances based on a remote display framework. μVNC networking software was experimentally implemented on an embedded processor and successfully provided Internet connectivity and interconnectivity of appliances. TV and VCR were both assembled with μVNC's and this TV set succeeded in VCR programming using a program code selected from a remote PC browser that projected to TV.
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  • The Home Networking System Based on IEEE1394 and Ethernet
    Yoshihiro Noguchi, Keiji Shimada, Hiroyuki Sasaki
    Article type: Article
    Session ID: CE2001-31
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_67
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In this paper, we propose the home networking system based on IEEE1394 and Ethernet. Our home networking system consists of low-power IEEE1394 and Ethernet wall-plate, multi-core POF and UTP Cat.5 combination cable, IEEE1394-Ethernet bridge router, and network control application based on Web server technologies. The targets of our home networking system are seamless operation between IEEE1394 and Ethernet, low-power, and low-cost.
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  • [title in Japanese]
    Article type: Appendix
    Pages App1-
    Published: September 21, 2001
    Released on J-STAGE: June 23, 2017
    DOIhttps://doi.org/10.11485/itetr.25.61.0_App1
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