All issues
Predecessor
26.63
Displaying 1-17 of 17 articles from this issue
- |<
- <
- 1
- >
- >|
-
Article type: Cover
Pages Cover1-
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (12K) -
Article type: Index
Pages Toc1-
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (71K) -
Amal Bandula KARIYAWASAM, Akira TAKASAKI, Kimihiro NISHIO, Hiroshi ABE ...Article type: Article
Session ID: IPU200269
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe have improved the tolerance of the edge detection network based on vertebrate outer retina for the threshold voltage and current factor variations of MOS transistors. Simulation results using the simulation program with integrated circuit emphasis (SPICE) indicated the weak tolerance of the edge detection network for the threshold voltage and current factor variations The novel edge detection circuit constructed with a feedback circuit that has superior tolerance for the MOS transistor mismatch. As a result of simulations, reduced influence for the variation of threshold voltage and the current factor was confirmed.View full abstractDownload PDF (634K) -
Hiroshi ABE, Kimihiro NISHIO, Akira TAKASAKI, Amal Bandula KARIYAWASAM ...Article type: Article
Session ID: IPU200270
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper describes fundamental concepts of an artificial retinal chip and the integration of the outer retina circuit producing edge information and the inner retina circuit producing motion information. In order to accomplish reasonable outputs of the circuit, we introduced Pulse Density Modulation (PDM) circuit based on ganglion cell layer, the final layer of the retina. The simulation results utilized SPICE showed that output currents of both inner circuit and outer circuit were converted to the pulses whose edge and motion information were encoded. These output pulses corresponded to the output signal of retinal ganglion cell.View full abstractDownload PDF (725K) -
Masahiro OHTANI, Hiroo YONEZUArticle type: Article
Session ID: IPU200271
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA biological model of vision systems in the lateral eye of limulus was implemented into a simple analog network. The vision system can extract temporal and spatial contrasts from visual scenes. The local signals of temporal and spatial contrasts at each ommatidium, which is a unit element of the lateral eye, are formed by using self-inihibition and lateral inhibition from neighbors, respectively. Simulation results using SPICE showed that the implemented network detected temporal and spatial contrasts expected from the model. The detection of temporal and spatial contrasts is a primitive function in early visual processing. Therefore, the proposed network has the potential to be a basic component of various visual preprocessors.View full abstractDownload PDF (823K) -
Keisuke INOUE, Kazuhiro SHIMONOMURA, Seiji KAMEDA, Tetsuya YAGIArticle type: Article
Session ID: IPU200272
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThe silicon retina is an analog CMOS VLSI which is designed to emulate the parallel circuit structure of the vertebrate retina. Inspired by the inner retinal circuit, we have developed a silicon retina which emulates two fundamental types of light-induced responses corresponding to the spatial and the temporal derivatives of the image. A real time target tracking was carried out using the silicon retina under an indoor illumination.View full abstractDownload PDF (748K) -
Tomochika HARADA, Tadayoshi ENOMOTOArticle type: Article
Session ID: IPU200273
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA source voltage-controlled oscillator (S-VCO), whose oscillating frequency f is controlled by a source voltage of MOSFET, has been developed. A phase-locked-loop (PLL) clock generator incorporating the S-VCO was fabricated by using 0.6-μm 2-poly 3-metal CMOS technology. The number of MOSFETs in the S-VCO is about 1/2 that in a conventional current-starved VCO. The voltage sensitivity of a fabricated 43-stage S-VCO with a single 3.3-V power supply (VD) is approximately 70.3 MHz/V. At 50.0 MHz oscillation and 3.3V power supply, the measured jitter was 418 psec (2.09 %).View full abstractDownload PDF (763K) -
Yoshiyuki SHIBAHARA, Masaru KOKUBOArticle type: Article
Session ID: IPU200274
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSThis paper presents a calibration method for a high-frequency PLL synthesizer. As the frequency of the PLL synthesizer becomes high, a voltage-to-frequency conversion gain of a voltage-controlled oscillator (VCO) must be increased and PLL become sensitive to noise. The voltage-to-frequency conversion gain can be reduced by applying constant bias current to VCO and making the VCO minimum frequency offset from the zero frequency. In the conventional method, however, according to the large device variation of CMOS process, it is difficult to satisfy the desired frequency range and PLL might fail to lock. In our work, a self-calibration technique has been applied to adjust the tuning range automatically into the desired frequency band. Simulation result shows that the voltage-to-frequency conversion gain is reduced to 25% of the conventional VCO.View full abstractDownload PDF (532K) -
Tomoaki MAEDA, Atsushi IWATAArticle type: Article
Session ID: IPU200275
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe propose how to optimize low phase noise and wide frequency range voltage-controlled oscillators (VCOs). The phase noise is in proportion to the square of oscillation frequency, and in inverse proportion to the square of oscillation amplitude. Therefore, the amplitude is usually designed large at desired frequency. But in case of wide frequency range, optimizing the amplitude in full range is difficult because amplitude is in proportion to the frequency. This paper describes effective circuits and design procedure for this problem. We successfully designed a monolithic VCO with on-chip spiral inductor by using 0.25μm CMOS technology. The simulated frequency range is 1.18GHz to 2.21GHz, and the phase noise are -110dBc/Hz, -107dBc/Hz, and -96dBc/Hz at 100kHz offset from 1.21GHz, 1.54GHz, and 2.21GHz carriers. The VCO dissipates 7mA from a 2.5-V supply voltage.View full abstractDownload PDF (612K) -
Kenji SUZUKI, Mamoru UGAJIN, Junichi KODATE, Tsuneo TSUKAHARAArticle type: Article
Session ID: IPU200276
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESS2-GHz-Band Highly Accurate On-chip Polyphase filters is presented. A rotational asymmetric configuration is adopted to improve the gain mismatches and phase errors of quadrature signals. Shielded metal layer, which is between polyphase filters and substrate of wafers, could reduce the substrate crosstalk, which causes the gain mismatches of quadrature signals. The measured amplitude mismatches and phase errors of the polyphase filters are 0.05 dB and 1 degree, respectively. An image rejection mixer, which composed of a quadrature mixer and the polyphase filters, achieves 40dB image rejection.View full abstractDownload PDF (721K) -
Yoshiharu KUDOH, Muneo FUKAISHI, Masayuki MIZUNOArticle type: Article
Session ID: IPU200277
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSEnhanced with LSI technology scaling, the frequency-dependent attenuation of the transmission lines between chips, PCBs, etc, becomes the obstacle to improve the system performance. Because, large frequency-dependent attenuation gives poor eye-opening and high bit-error rate in data transmission. This paper presents a 5-Gb/s 10-meter 28AWG cable transceiver by using 0.13-μm CMOS technologies. In this transceiver, a continuous-time post-equalizer with recently developed no-feedback-loop high-speed analog amplifiers can handle up to 9 dB of frequency-dependent attenuation in cables, and an 18-dB improvement in the attenuation (27 dB in total) can also be achieved by using the pre- and post-equalization techniques in combination.View full abstractDownload PDF (719K) -
Yoshitomo KANEDA, Tomohisa WADA, Shuji MURAKAMI, Kunio MORIMOTO, Michi ...Article type: Article
Session ID: IPU200278
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSIn a digital-communications system, a receiver presume channel distortion and remove them away from received signals after demodulating. In the latter part, error correction processing is performed and then desired data is obtained. By channel estimation, it is passible to judge that the error rate is large in large channel distortion, and the error rate is small in small channel distortion. Therefore, it is possible to improve the whole error correction capability by presuming the reliability (Confidence) from channel distortion, and utilizing the value as Confidence Factor [1] in a latter error correction block(FEC). This paper takes Digital Terrestrial Television Broad-casting System as an example, and shows the method that Confidence Factor generated in the receiver block works effectively at the Viterbi decoder on the assumption that it consists of an OFDM demodulation and soft decision Viterbi decoder. The simulation result using MATLAB Simulink and the demonstration system designed on FPGA are described as performance evaluation.View full abstractDownload PDF (715K) -
Yukinori AKAMINE, Hirotake ISHII, Satoshi TANAKA, Kazuaki HORI, Akio Y ...Article type: Article
Session ID: IPU200279
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA W-CDMA mobile terminal test system which include RF TX-IC, RX-IC and baseband modem is evaluated on 3GPP TS34.121. Section 5 & 6. The receiver architecture is direct conversion and the transmitter architecture is 2-stepup conversion. The test system achieves adjacent channel leakage power of 41dBc (Spec. >33 dBc), modulation accuracy of <17.5% (Spec. <17.5 %), reference sensitivity of -118.3 dBm (Spec. <-117 dBm), and blocking characteristics of -117.8 dBm (Spec. <-114 dBm). Those performance is suitable for W-CDMA mobile phone system.View full abstractDownload PDF (761K) -
Taichiro KATO, Shoji KAWAHITO, Koji KOBAYASHI, Hirosi SASAKI, Tatsuya ...Article type: Article
Session ID: IPU200280
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSA binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is presented. Therty-two compact cyclic pipelined analog-to-digital converters are integrated. The image sensor produces a 16 x 16 range image from a pair of 256 x 256 images, together with the dedicated pipelined FFT processor, at 300 frames/s.View full abstractDownload PDF (667K) -
Design of new smart image sensor which has two focal planes for object tracking and depth estimationShoichi NAGAO, Takayuki HAMAMOTOArticle type: Article
Session ID: IPU200281
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSWe propose a smart sensor which has two focal planes on one chip. This sensor produces 1bit flag signals which indicate the position of moving area. And by using only this flag signals, tracking of moving object and estimation of the depth can be done in real time. In this paper, we describe the simulation results by using FPGA and two smart sensors, and the circuit design of the new smart sensor.View full abstractDownload PDF (664K) -
Article type: Appendix
Pages App1-
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (73K) -
Article type: Appendix
Pages App2-
Published: September 27, 2002
Released on J-STAGE: June 23, 2017
CONFERENCE PROCEEDINGS FREE ACCESSDownload PDF (73K)
- |<
- <
- 1
- >
- >|