ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
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32.45
Displaying 1-34 of 34 articles from this issue
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  • [title in Japanese]
    Article type: Cover
    Pages Cover1-
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_Cover1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Index
    Pages Toc1-
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_Toc1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Foreground-Calibration A/D Converter with LMS Algorithm
    Tomomi Takahashi, Takashi Oshima, Taizo Yamawaki
    Article type: Article
    Session ID: IST2008-43
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_1
    CONFERENCE PROCEEDINGS FREE ACCESS
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    It is demanded that future wireless applications that need high data rate above 1 Gbps have A/D converter that achieves high resolution above 10 b, high sampling rate more than several hundreds of MS/s and low power consumption. For this approach, digital calibration A/D converter has gathered attention. In this report, we propose Foreground-calibration A/D converter that suits for wireless transceiver RF-IC for TDD system. It is shown by macro-based simulation that A/D conversion can be achieved with high convergence ability in proposed calibration method.
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  • A 15b pipeline ADC using non-slewing amplifiers and digital calibration of incomplete settling errors
    Shoji Kawahito, Kazutaka HONDA, Zheng LIU, Keita YASUTOMI, Sinya ITOH
    Article type: Article
    Session ID: IST2008-44
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_7
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A 15b power-efficient pipeline A/D converter using capacitance-coupling non-slewing amplifiers is presented. A modified 1.5b/stage transfer curve combined with the non-slewing amplifier is useful for the error corrections of incomplete settling error. The relationship between the input signal and the incomplete settling errors can be linearized and the errors can be corrected in digital domain with a simple calculation. A prototype ADC fabricated in 0.25μm process consumes 123mW at 30MSample/s and 2.5V power supply. The SNDR and the SFDR at 30MS/s are 75.0 dB and 86.5 dB, respectively with the incomplete settling error corrections.
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  • A synthesize method of continuous-time delta-sigma modulator using new high-order integrators
    Shiro Dosho, Kazuo Matsukawa, Yousuke Mitani, Masao Takayama, Kouji Ob ...
    Article type: Article
    Session ID: IST2008-45
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_13
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Recently, continuous time delta-sigma modulators are widely studied, because its switch-less architecture enables wide band operation even if a power supply voltage is low. In this paper, high-order integrators are newly developed in order to reduce the number of operational amplifiers used in the integrator path of the delta-sigma modulators. The high order modulator is applicable for both multiple feedback and feed forward compensation architectures. The design example of 5^<th> order delta sigma modulator composed of 2^<nd> order integrators is detailed.
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  • A Linearity Improvement Technique for Cyclic D/A Converters
    Wataru Saito, Hidenao Kobayashi, Tetsuya Matsumoto, Michio Yotsuyanagi
    Article type: Article
    Session ID: IST2008-46
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_19
    CONFERENCE PROCEEDINGS FREE ACCESS
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    This paper presents a calibration technique suitable for Cyclic D/A Converters (DAC) which improves Differential Non Linearity (DNL) to guarantee DAC's monotonicity. We confirmed 10bit Cyclic DACs fabricated in a 90nm CMOS process could operate as 12bit accuracy after applying this technique.
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  • A 14-bit CMOS DAC with Current Sources Free from Ground-Line drop and with Output Circuits Free form Code-dependent Variable Time Constant
    Takuya KOISO, Yasuhiro SUGIMOTO
    Article type: Article
    Session ID: IST2008-47
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_25
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    Circuit techniques for realizing a highly accurate and high-speed CMOS DAC are described. Firstly, we realized the current source matrix with 14-bit resolution adopting a new structure that eliminates the influence of the voltage drop caused by the line resistance. Next, we confirmed that the time-constant change of the output terminal depending on the digital input code deteriorates SFDR, and propose the output circuit that suppresses the time-constant change.
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  • Optimum Design Considerations for a CMOS Amplifier and Efficiency of a class-AB Structure
    Masayuki UNO, Shoji KAWAHITO
    Article type: Article
    Session ID: IST2008-48
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_31
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    This paper describes design considerations for a CMOS amplifier to meet a frequency specification at the minimum current-consumption. Minimum bias current and optimum transistor sizes of a basic differential amplifier can be determined using parameters of output parasitic capacitances and load capacitances if the input transistors operate in strong inversion region. It can be approximately estimated in cases of weak inversion and moderate inversion operations. Class-AB differential amplifiers are also examined and a potential current reduction of them is indicated.
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  • High-Speed Low-Power CMOS Quantizer with Digital Calibration
    Yoshie HARADA, Yoshihiro MASUI, Takeshi YOSHIDA, Atsushi IWATA
    Article type: Article
    Session ID: IST2008-49
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_37
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A 1GHz sampling and 4bit resolution flash quantizer applied to a wideband ΔΣ analog-to-digital converter was developed with a 90nm CMOS technology. In order to achieve high speed and low power consumption, a latch comparator core was design with small size MOS devices, and quantization level error was calibrated by binary capacity arrays weighted by data automatically obtained by successive approximation algorithm. By measurement of the test chip, dissipation power of 1.13mW at 600MHz and 1.0V supply operation and the maximum clock frequency of 1.5GHz were obtained. The Integral Non Linearity (INL) which was 1.24LSB before calibration was improved to 0.22LSB by the calibration.
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  • A Study of Simulation Technique Using MATLAB/Simulink for a DC-DC Converter
    Chihiro KAWABATA, Yasuhiro SUGIMOTO
    Article type: Article
    Session ID: IST2008-50
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_43
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Currently, in the design of a DC-DC converter, a simulator such as SPICE is generally used. Although SPICE provides precise simulation results, there exists problems in the simulation of the DC-DC converter such that "the simulation time of a transient analysis is long", and "frequency characteristics can not be obtained in the normal way." In this paper we propose the use of MATLAB/Simulink to solve those problems. The details are described below.
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  • Process compensation techniques for low-voltage CMOS digital circuits
    Yusuke TSUGITA, Ken UENO, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEM ...
    Article type: Article
    Session ID: IST2008-51
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_49
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    In low-voltage CMOS digital circuits, threshold voltage varaition fluctuates circuit performance significantly. In this work, on-chip process compensation techniques for low-voltage CMOS digital circuits were proposed. We employed on-current compensation tehchniques in a digital circuit by using a reference current, that is independent of process variations. In addition, the technique can be applied to circuit performance's fluctuation induced by temperature change. We confirmed the operation of the circuit by a SPICE simulation with a set of 0.35-μm standard CMOS parameters, and performed Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs. SPICE simulation demonstrated that the process variations of digital circuits were improved to 65% by applying the proposed architecture. The techniques will be useful for on-chip process compensation of digital circuits.
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  • An Ultra-low Power Voltage Reference Circuit consisting of Subthreshold MOSFETs
    Ken UENO, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA
    Article type: Article
    Session ID: IST2008-52
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_55
    CONFERENCE PROCEEDINGS FREE ACCESS
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    An ultra-low power CMOS voltage reference circuit has been fabricated in 0.35-μm standard CMOS process. The circuit generates a reference voltage based on threshold voltage of a MOSFET at absolute zero temperature. Theoretical analyses and experimental results showed that the circuit generates a quite stable reference voltage of 745 mV on average. The temperature coefficient and line sensitivity of the circuit were 7 ppm/℃ and 20 ppm/V, respectively. The power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The circuit consists of subthreshold MOSFETs with a low-power dissipation of 0.3μW or less, and a 1.5-V power supply. Because the circuit generates a reference voltage based on threshold voltage of a MOSFET in an LSI chip, it can be used as an on-chip process monitoring circuit and a part of the on-chip process compensation circuit systems.
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  • Implementation and evaluation of image sensor with high-speed 2D motion detection by single-pixel matching
    Atsunori SHIKINO, Kenichi NAKAYAMA, Toshiyuki SUGITA, Takayuki HAMAMOT ...
    Article type: Article
    Session ID: IST2008-53
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_61
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In this paper, we propose a method of motion detection by single-pixel matching implemented on a smart image sensor, and report the design and evaluation of the prototype chip. The proposed method can detect the 2D moving vector into a limited area and by using high inter-frame correlation at high frame rate of 1000fps. The method can be achieved in small column-parallel circuits on the sensor and by low power consumption.
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  • A Linear Response 200-dB Dynamic Range CMOS Image Sensor with Multiple Voltage and Current Readout Operations
    Noriko IDE, Nana AKAHANE, Shigetoshi SUGAWA
    Article type: Article
    Session ID: IST2008-54
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_67
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Operation methods for high frame rate, linear response, wide dynamic range (DR) and high S/N ratio in a CMOS image sensor are discussed. The color CMOS image sensor which consists of the 1/3-inch, 800^H×600^V pixels and 5.6-μm pixel pitch has been fabricated by 0.18-μm 2P3M CMOS technology. The image sensor operates the total frame rate of 1/13-sec with three-time voltage readout operations and one current readout operation and have realized full linear photoelectric conversion responses, 26-dB S/N ratio for the image of the 18-% gray card at all integration operation switching points and the 207-dB DR.
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  • A source-modulated pulse-width-modulation CMOS imager for biomedical applications
    Sanahiro SHISHIDO, Kiyotaka SASAGAWA, Keiichiro KAGAWA, Takashi TOKUDA ...
    Article type: Article
    Session ID: IST2008-55
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_73
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Our goal of research is to achieve a low voltage and low power consumption CMOS image sensor for biomedical applications. We develop the image sensor using pulse-width-modulation scheme that converts voltage change at the photodiode to the pulse width by use of an in-pixel gate-common amplifier. In the previous work we have successfully demonstrated the operation of the PWM sensor with 128^H×96^V pixels under 1.35-V single supply voltage. In this report, we describe some design considerations and formulated about IR drop effect of the PWM sensor. We have designed and fabricated a a CIF (368^H×320^V pixels) size CMOS image sensor with low-voltage low-power-consumption using the PWM pixel readout scheme under 1.2-V single-power-supply voltage.
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  • [title in Japanese]
    [in Japanese], [in Japanese], [in Japanese], [in Japanese], [in Japane ...
    Article type: Article
    Session ID: IST2008-56
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_77
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • Toward Variability-Aware Design
    HIDETOSHI ONODERA
    Article type: Article
    Session ID: IST2008-57
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_83
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    As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in LSI design. In this report, measured variabilities from 0.35μm to 90nm processes are explained with a growing concern of within-die components. Variability impact on circuit performance is discussed. A possible approach for mitigating the variability is the introduction of layout regularity, and its effect is examined by test structures in a 90nm process and lithography simulation in a 45nm process. Our observation suggests that, from the standpoint of performance overhead incurred by the regularity enhancement, it is important to correctly enforce necessary and sufficient level of regularity for each technology node.
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  • Analog / RF performance of scaled MOSFET : Is scaled MOSFET friend for analog / RF circuits?
    Tatsuya Ohguro
    Article type: Article
    Session ID: IST2008-58
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_89
    CONFERENCE PROCEEDINGS FREE ACCESS
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    High performance has been realized by gate length scaling of MOSFET. Recently, not only gate length scaling but also aggressive advanced technology has been introduced for high performance MOSFET. Those are increase of mobility due to stress for the channel, decrease of gate leakage current by using high K dielectric material and suppression of gate depletion by introducing metal gate electrode. In this paper, the affection to analog / RF performance from those techniques are presented.
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  • Random Telegraph Signal Noises in Small MOS Devices
    Shigetoshi SUGAWA
    Article type: Article
    Session ID: IST2008-59
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_95
    CONFERENCE PROCEEDINGS FREE ACCESS
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    For random telegraph signal (RTS) noises generated in small MOS devices, using a large array TEG, a gate insulator material dependence, an antenna ratio dependence, RTS noises when the source is replaced with the drain, and correlations of RTS noises generated by gate leakage current and drain-source current after gate high field stress is applied have been reported.
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  • Analog design issues of a high-resolution and low-power ADC using a low voltage supply and a deep sub-micron process
    Kunihiko Gotoh
    Article type: Article
    Session ID: IST2008-60
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_101
    CONFERENCE PROCEEDINGS FREE ACCESS
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    The demand for high-speed (≧30 MS/s), high-resolution (≧10 bit) and low-power operation analog-to-digital converters (ADC) is increasing because of the rapid growth in digital consumer applications (e.g., DTV and DSC) and wireless communications. Recently, the hardware in these applications has been developed with system on a chip (SoC) devices that incorporate deep sub-micron CMOS processes. Furthermore, an accurate operation at a low supply (under 1.2 V) is also required of these devices. But. it is a challenging task to design a high-accuracy and low-power ADC to operate under 1.2-V supply, because of the reduction of the input signal range. In the case of a low input signal range, the sampling capacitor value and the analog current of the op-amp used in the ADC must be increased because the thermal noise (kT/C) must be reduced to correspond with the scaling-down of the input signal power. This means that the analog power consumption and die size of the ADC increases in spite of using a low supply voltage and a deep sub-micron CMOS process. This paper describes analog design issues using a low voltage supply and a deep sub-micron process for a pipelined ADC, and introduces some new approaches on solving these problems with the pipelined ADC.
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  • Direction for High Performance Analog Circuit Integration
    Toshihiko Hamasaki
    Article type: Article
    Session ID: IST2008-61
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_107
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Advanced CMOS technology beyond 90nm is leading power reduction trend in analog digital mixed signal circuitry and SOC as well. Focused application spaces of mixed signal SOC are portable devices such as cellular and the other consumer gadgets. FOM of ADC performance has drastically been improved as presented in last three years ISSCC. On the other hand, leading edge performance analog oriented device is still fabricated by BiCMOS technology for higher speed and conventional MOS such as >0.18um for higher resolution, respectively. In this paper, the integration trend of high performance analog is discussed based on the performance requirement of transistors and components.
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  • An Optimization Design of Temperature Sensor Including Device Fluctuation
    Hideyuki TAJIMA, Tetsuhiro KOYAMA, Motoi YAMAGUCHI, Masaaki SOUDA, Mic ...
    Article type: Article
    Session ID: IST2008-62
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_113
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We show an optimization design of temperature sensor which keeps the temperature error fluctuation within a desired fluctuation and minimize the area. We express the transfer function of temperature error fluctuation as the device fluctuation function by establishing a system model of the circuit and replacing the device fluctuation function to the area function by using pelgrom coefficient. Thereby the transfer function of the temperature error fluctuation expresses an area function. It is possible to keep the temperature error fluctuation within a desired fluctuation without useless area increase by analyzing the trade-off between the area and the temperature error fluctuation theoretically using this transfer function of the temperature error fluctuation expressed as an area function. As a result, we kept 3σ of the temperature error fluctuation within ±1.4℃ from +50 to +125℃ against design value ±3.6℃, and the area was 0.37mm^2 (including IO). By this fact, we proved this design method was effective.
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  • Active Stress Sensor using SOI-MOSFET
    Tomochika HARADA, Yusuke Kamiya, Sumio OKUYAMA, Koichi MATSUSHITA
    Article type: Article
    Session ID: IST2008-63
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_119
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Integrated pressure sensors based on piezoresistance effect are made by various materials and devices, such as diffusion resistor, metal resistor and capacitor. A signal processing circuit is necessary for integrated pressure sensors to achieve high S/N ratio. If pressure sensors can be constructed only MOSFETs, it is not necessary to use other signal processing circuit because it can be operated both stress sensing and signal processing. Thus, we estimate to achieve low-power consumption and high density integration sensors. In this paper, as a fundamental research of active stress sensor which operates both signal processing and sensing, we design and fabricate active stress sensors using SOI-MOSFETs and MEMS technology for integrated intelligent pressure sensors.
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  • Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring
    Yuuki ARAGA, Takushi HASHIDA, Makoto NAGATA
    Article type: Article
    Session ID: IST2008-64
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_125
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Multi-channel waveform monitoring system for large-scale SoCs. The system consists of probing front end circuits and a waveform acquisition kernel. In this paper, we constructed an on-chip waveform capturing system. We evaluated throughput of digitization and linearity of monitor system, which are the most important performance measures. The proposed algorithm reduces 92.2% of transactions from a conventional algorithm, and demonstrates 59.1dB SFDR, 51.5dB SNDR and 8.2 ENOB at 200 Ms/s for 25-MHz bandwidth.
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  • A retinal prosthesis platform for a subretinal implantation
    Keisuke YAGYU, Kiyotaka SASAGAWA, Keiichiro KAGAWA, Takashi TOKUDA, Ju ...
    Article type: Article
    Session ID: IST2008-65
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_131
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We are developing an artificial vision device to restore vision for the blind by electrically stimulating retinal tissue. We propose a retinal prosthesis that includes artificial vision devices with functions of signal processing, optical detection and electrical stimulation. In the proposed retinal prosthesis, an optical signal is processed and converted to a stimulus current suitable for restoring vision by an arithmetic circuit in the device. In this paper, we describe the functions of proposed retinal prosthesis. In addition, we designed and characterized TEG (Test Element Group) circuits, which are the core blocks and PFM (Pulse Frequency Modulation) photo sensor in standard 0.35-μm CMOS process.
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  • Variable bandwidth digital bandpass filter for cognitive radio
    Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Takashi Takeuchi, Hiroshi ...
    Article type: Article
    Session ID: IST2008-66
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_137
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • All-digital 300-MHz-band transceiver LSI and its application to a low-power wireless sensor node
    Kenji SUZUKI, Mamoru UGAJIN, Mitsuru HARADA
    Article type: Article
    Session ID: IST2008-67
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_143
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    Wireless sensor networks, which monitor the environments, require many small and low-power-consumption sensor nodes. In this work, to fabricate such sensor nodes, we implemented in a prototype IC an all-digital RF-transmitting scheme. The IC, which operates with a voltage of 3 V and a current of 1.6 μA, sends data intermittently and achieves long-distance communication of the order of 10 m with a 1-Mbps data rate. Since the ratio of intermittent operation is approximately 530, the average bit rate is equal to 1.8 kbps. A prototype wireless sensor node, which contains the IC and a conventional vibration sensor, demonstrates the feasibility of long-battery-life sensor nodes.
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  • A 100Mbps, 0.41mV Impulse UWB Transceiver Based on Leading Edge Detection Technique
    Lechang LIU, Yoshio MIYAMOTA, Zhiwei ZHOU, Kosuke SAKAIDA, Jisun RYU, ...
    Article type: Article
    Session ID: IST2008-68
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_149
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    A novel low power impulse Ultra-wideband (UWB) transceiver based on leading edge detection technique is developed. It features a digital pulse-shaping transmitter, a DC power-free pulse discriminator and an error-recovery phase-frequency detector. The developed transceiver in 90nm CMOS achieves the lowest energy consumption of 2.2pJ/bit transmitter and 1.9pJ/bit receiver at 100Mbps.
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  • 10-Gbit/s Data-Timing Generator IC using jitter-reduction circuits with spectrum conversion
    Tomoaki Kawamura, Yusuke Ohtomo
    Article type: Article
    Session ID: IST2008-69
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_155
    CONFERENCE PROCEEDINGS FREE ACCESS
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    A data-timing generator IC (DTG) provides a delay of over 2 ns, and operates over the wide frequency range of DC to 11 Gbit/s. By using a spectrum-conversion technique that suppresses the effect of the group-delay deviation of the delay gates, the output jitter is reduced to one-third that of a conventional DTG. The total peak-to-peak jitter of a 2-ns delayed 10-Gbit/s pseudo-random bit stream of 2^<31>-1 output data is 12 ps_<pp> including 7 ps_<pp> of input-data jitter. The DTG is fabricated using a 0.25-μm SiGe BiCMOS process and consumes 2.5 W from a 3.3-V supply.
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  • Design of Low-Power Oscillator for Medical Devices
    Kennichi Matsunaga, Takashi Kurashina, Akira Matsuzawa
    Article type: Article
    Session ID: IST2008-70
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_159
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    We have studied the requirements and circuit architecture of bladder pressure measurement system. To realize low power operation, decreasing the operating frequency of the micro computer is necessary. We show ring oscillator is an appropriate clocking topology to control the operating frequency. We also propose a system for frequency synchronization between inside and outside of our body, using pulse injection locking and verify the applicability of it through simulations. The results of the simulation shows ±10% supply voltage variation can be absorbed by the system without induce deterministic jitter.
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  • [title in Japanese]
    [in Japanese], [in Japanese], [in Japanese], [in Japanese]
    Article type: Article
    Session ID: IST2008-71
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_165
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Appendix
    Pages App1-
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_App1
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  • [title in Japanese]
    Article type: Appendix
    Pages App2-
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_App2
    CONFERENCE PROCEEDINGS FREE ACCESS
    Download PDF (78K)
  • [title in Japanese]
    Article type: Appendix
    Pages App3-
    Published: October 22, 2008
    Released on J-STAGE: September 20, 2017
    DOIhttps://doi.org/10.11485/itetr.32.45.0_App3
    CONFERENCE PROCEEDINGS FREE ACCESS
    Download PDF (78K)
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